Automatic simulation method for functional equivalence check
In the mixed-signal chip, behavioral model is widely used to describe the behavior of the analog/mixed-signal blocks in Verilog/Systemverilog/VHDL so as to facilitate the fullchip netlisting for the fullchip Verilog simulation. In order to ensure correct，effective and comprehensine function verifica...
| Autori principali: | , , , , , , , |
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| Natura: | Articolo |
| Lingua: | zho |
| Pubblicazione: |
National Computer System Engineering Research Institute of China
2019-08-01
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| Serie: | Dianzi Jishu Yingyong |
| Soggetti: | |
| Accesso online: | http://www.chinaaet.com/article/3000107412 |