Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches
STT-RAM (Spin-Transfer Torque Random Access Memory) appears to be a viable alternative to SRAM-based on-chip caches. Due to its high density and low leakage power, STT-RAM can be used to build massive capacity last-level caches (LLC). Unfortunately, STT-RAM has a much longer write latency and a much...
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MDPI AG
2022-01-01
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Online Access: | https://www.mdpi.com/2079-9292/11/2/240 |
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author | Beomjun Kim Yongtae Kim Prashant Nair Seokin Hong |
author_facet | Beomjun Kim Yongtae Kim Prashant Nair Seokin Hong |
author_sort | Beomjun Kim |
collection | DOAJ |
description | STT-RAM (Spin-Transfer Torque Random Access Memory) appears to be a viable alternative to SRAM-based on-chip caches. Due to its high density and low leakage power, STT-RAM can be used to build massive capacity last-level caches (LLC). Unfortunately, STT-RAM has a much longer write latency and a much greater write energy than SRAM. Researchers developed hybrid caches made up of SRAM and STT-RAM regions to cope with these challenges. In order to store as many write-intensive blocks in the SRAM region as possible in hybrid caches, an intelligent block placement policy is essential. This paper proposes an adaptive block placement framework for hybrid caches that incorporates metadata embedding (ADAM). When a cache block is evicted from the LLC, ADAM embeds metadata (i.e., write intensity) into the block. Metadata embedded in the cache block are then extracted and used to determine the block’s write intensity when it is fetched from main memory. Our research demonstrates that ADAM can enhance performance by 26% (on average) when compared to a baseline block placement scheme. |
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institution | Directory Open Access Journal |
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language | English |
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publishDate | 2022-01-01 |
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spelling | doaj.art-fc3ce4d85ccd44fd8aa6eab724fd8de42023-11-23T13:34:34ZengMDPI AGElectronics2079-92922022-01-0111224010.3390/electronics11020240Exploiting Data Compression for Adaptive Block Placement in Hybrid CachesBeomjun Kim0Yongtae Kim1Prashant Nair2Seokin Hong3School of Computer Science and Engineering, Kyungpook National University, Daegu 41566, KoreaSchool of Computer Science and Engineering, Kyungpook National University, Daegu 41566, KoreaDepartment of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC V6T 1Z4, CanadaDepartment of Semiconductor Systems Engineering, Sungkyunkwan University, Suwon 16419, KoreaSTT-RAM (Spin-Transfer Torque Random Access Memory) appears to be a viable alternative to SRAM-based on-chip caches. Due to its high density and low leakage power, STT-RAM can be used to build massive capacity last-level caches (LLC). Unfortunately, STT-RAM has a much longer write latency and a much greater write energy than SRAM. Researchers developed hybrid caches made up of SRAM and STT-RAM regions to cope with these challenges. In order to store as many write-intensive blocks in the SRAM region as possible in hybrid caches, an intelligent block placement policy is essential. This paper proposes an adaptive block placement framework for hybrid caches that incorporates metadata embedding (ADAM). When a cache block is evicted from the LLC, ADAM embeds metadata (i.e., write intensity) into the block. Metadata embedded in the cache block are then extracted and used to determine the block’s write intensity when it is fetched from main memory. Our research demonstrates that ADAM can enhance performance by 26% (on average) when compared to a baseline block placement scheme.https://www.mdpi.com/2079-9292/11/2/240last-level cachehybrid cachenon-volatile memorySTT-RAM |
spellingShingle | Beomjun Kim Yongtae Kim Prashant Nair Seokin Hong Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches Electronics last-level cache hybrid cache non-volatile memory STT-RAM |
title | Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches |
title_full | Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches |
title_fullStr | Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches |
title_full_unstemmed | Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches |
title_short | Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches |
title_sort | exploiting data compression for adaptive block placement in hybrid caches |
topic | last-level cache hybrid cache non-volatile memory STT-RAM |
url | https://www.mdpi.com/2079-9292/11/2/240 |
work_keys_str_mv | AT beomjunkim exploitingdatacompressionforadaptiveblockplacementinhybridcaches AT yongtaekim exploitingdatacompressionforadaptiveblockplacementinhybridcaches AT prashantnair exploitingdatacompressionforadaptiveblockplacementinhybridcaches AT seokinhong exploitingdatacompressionforadaptiveblockplacementinhybridcaches |