SYSTEM PARALLELISATION FOR COMPUTER VISION - Asaad A. M. AL-Sudani (Journal of Engineering, 2003)
This paper delineates the parallelisation of a computer vision system. It presents the system proposal and the relevant design phases of a laboratory based model. This model involves special purpose hardware implementing the early stages of processing with very high data rate. It Incorporates facilities enabling the user to capture, retain, retrieve, compare, and analyse video images. The output of this hardware is to be processed by a software running in a parallel processor. The latter is a VMEbus-based multiprocessing machine accommodating the system hardware and ensures for better flexibility. It also participates in a reasonable distribution of the systern processing power. The kernel philosophy here depends on the concept of modularisation to attain higher degree of design consistency. It believes that the spatiotemporal pixel variation of two adjacent video frames involves sufficient information to detect movement. This implies pixel encoding and motion parameters estimation. The system software is based on a data compressive technique (Strip Encoding of Adjacent Frames) to solve the bottlenecks problem in the whole system throughput. The research hereby attempts to attain a match in the degree of sophistication between the system hardware and software structures. This yields to make the system processing power better meets the system applications requirements. The research investigates the above presented design phases along with their logical, functional, technical, and modular specifications. The research is adequate for development in a wide range of applications (requiring parallel architectures for image processing) like: Artificial Intelligence, Features Extraction and Pattern Recognition, Expert Systems, Computer Vision and Robotic Vision, Industrial Control, and other civil and military applications.