TReMo+: Modeling Ternary and Binary ReRAM-Based Memories With Flexible Write-Verification Mechanisms
Non-volatile memory (NVM) technologies offer a number of advantages over conventional memory technologies such as SRAM and DRAM. These include a smaller area requirement, a lower energy requirement for reading and partly for writing, too, and, of course, the non-volatility and especially the qualita...
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Frontiers Media S.A.
2021-12-01
|
| Series: | Frontiers in Nanotechnology |
| Subjects: | |
| Online Access: | https://www.frontiersin.org/articles/10.3389/fnano.2021.765947/full |
| _version_ | 1818573560015224832 |
|---|---|
| author | Shima Hosseinzadeh Mehrdad Biglari Dietmar Fey |
| author_facet | Shima Hosseinzadeh Mehrdad Biglari Dietmar Fey |
| author_sort | Shima Hosseinzadeh |
| collection | DOAJ |
| description | Non-volatile memory (NVM) technologies offer a number of advantages over conventional memory technologies such as SRAM and DRAM. These include a smaller area requirement, a lower energy requirement for reading and partly for writing, too, and, of course, the non-volatility and especially the qualitative advantage of multi-bit capability. It is expected that memristors based on resistive random access memories (ReRAMs), phase-change memories, or spin-transfer torque random access memories will replace conventional memory technologies in certain areas or complement them in hybrid solutions. To support the design of systems that use NVMs, there is still research to be done on the modeling side of NVMs. In this paper, we focus on multi-bit ternary memories in particular. Ternary NVMs allow the implementation of extremely memory-efficient ternary weights in neural networks, which have sufficiently high accuracy in interference, or they are part of carry-free fast ternary adders. Furthermore, we lay a focus on the technology side of memristive ReRAMs. In this paper, a novel memory model in the circuit level is presented to support the design of systems that profit from ternary data representations. This model considers two read methods of ternary ReRAMs, namely, serial read and parallel read. They are extensively studied and compared in this work, as well as the write-verification method that is often used in NVMs to reduce the device stress and to increase the endurance. In addition, a comprehensive tool for the ternary model was developed, which is capable of performing energy, performance, and area estimation for a given setup. In this work, three case studies were conducted, namely, area cost per trit, excessive parameter selection for the write-verification method, and the assessment of pulse width variation and their energy latency trade-off for the write-verification method in ReRAM. |
| first_indexed | 2024-12-15T00:12:58Z |
| format | Article |
| id | doaj.art-fd045606b5c544998ada20bb0d6b3555 |
| institution | Directory Open Access Journal |
| issn | 2673-3013 |
| language | English |
| last_indexed | 2024-12-15T00:12:58Z |
| publishDate | 2021-12-01 |
| publisher | Frontiers Media S.A. |
| record_format | Article |
| series | Frontiers in Nanotechnology |
| spelling | doaj.art-fd045606b5c544998ada20bb0d6b35552022-12-21T22:42:31ZengFrontiers Media S.A.Frontiers in Nanotechnology2673-30132021-12-01310.3389/fnano.2021.765947765947TReMo+: Modeling Ternary and Binary ReRAM-Based Memories With Flexible Write-Verification MechanismsShima HosseinzadehMehrdad BiglariDietmar FeyNon-volatile memory (NVM) technologies offer a number of advantages over conventional memory technologies such as SRAM and DRAM. These include a smaller area requirement, a lower energy requirement for reading and partly for writing, too, and, of course, the non-volatility and especially the qualitative advantage of multi-bit capability. It is expected that memristors based on resistive random access memories (ReRAMs), phase-change memories, or spin-transfer torque random access memories will replace conventional memory technologies in certain areas or complement them in hybrid solutions. To support the design of systems that use NVMs, there is still research to be done on the modeling side of NVMs. In this paper, we focus on multi-bit ternary memories in particular. Ternary NVMs allow the implementation of extremely memory-efficient ternary weights in neural networks, which have sufficiently high accuracy in interference, or they are part of carry-free fast ternary adders. Furthermore, we lay a focus on the technology side of memristive ReRAMs. In this paper, a novel memory model in the circuit level is presented to support the design of systems that profit from ternary data representations. This model considers two read methods of ternary ReRAMs, namely, serial read and parallel read. They are extensively studied and compared in this work, as well as the write-verification method that is often used in NVMs to reduce the device stress and to increase the endurance. In addition, a comprehensive tool for the ternary model was developed, which is capable of performing energy, performance, and area estimation for a given setup. In this work, three case studies were conducted, namely, area cost per trit, excessive parameter selection for the write-verification method, and the assessment of pulse width variation and their energy latency trade-off for the write-verification method in ReRAM.https://www.frontiersin.org/articles/10.3389/fnano.2021.765947/fullmemristorternary systemanalytical circuit modelReRAMternary memory modelnon-volatile memory |
| spellingShingle | Shima Hosseinzadeh Mehrdad Biglari Dietmar Fey TReMo+: Modeling Ternary and Binary ReRAM-Based Memories With Flexible Write-Verification Mechanisms Frontiers in Nanotechnology memristor ternary system analytical circuit model ReRAM ternary memory model non-volatile memory |
| title | TReMo+: Modeling Ternary and Binary ReRAM-Based Memories With Flexible Write-Verification Mechanisms |
| title_full | TReMo+: Modeling Ternary and Binary ReRAM-Based Memories With Flexible Write-Verification Mechanisms |
| title_fullStr | TReMo+: Modeling Ternary and Binary ReRAM-Based Memories With Flexible Write-Verification Mechanisms |
| title_full_unstemmed | TReMo+: Modeling Ternary and Binary ReRAM-Based Memories With Flexible Write-Verification Mechanisms |
| title_short | TReMo+: Modeling Ternary and Binary ReRAM-Based Memories With Flexible Write-Verification Mechanisms |
| title_sort | tremo modeling ternary and binary reram based memories with flexible write verification mechanisms |
| topic | memristor ternary system analytical circuit model ReRAM ternary memory model non-volatile memory |
| url | https://www.frontiersin.org/articles/10.3389/fnano.2021.765947/full |
| work_keys_str_mv | AT shimahosseinzadeh tremomodelingternaryandbinaryrerambasedmemorieswithflexiblewriteverificationmechanisms AT mehrdadbiglari tremomodelingternaryandbinaryrerambasedmemorieswithflexiblewriteverificationmechanisms AT dietmarfey tremomodelingternaryandbinaryrerambasedmemorieswithflexiblewriteverificationmechanisms |