A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator
Sampling-based PLLs have become a new research trend due to the possibility of removing the frequency divider (FDIV) from the feedback path, where the FDIV increases the contribution of in-band noise by the factor of dividing ratio square (N<sup>2</sup>). Between two possible sampling me...
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-10-01
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| Series: | Sensors |
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| Online Access: | https://www.mdpi.com/1424-8220/21/20/6824 |
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| author | Jae-Soub Han Tae-Hyeok Eom Seong-Wook Choi Kiho Seong Dong-Hyun Yoon Tony Tae-Hyong Kim Kwang-Hyun Baek Yong Shim |
| author_facet | Jae-Soub Han Tae-Hyeok Eom Seong-Wook Choi Kiho Seong Dong-Hyun Yoon Tony Tae-Hyong Kim Kwang-Hyun Baek Yong Shim |
| author_sort | Jae-Soub Han |
| collection | DOAJ |
| description | Sampling-based PLLs have become a new research trend due to the possibility of removing the frequency divider (FDIV) from the feedback path, where the FDIV increases the contribution of in-band noise by the factor of dividing ratio square (N<sup>2</sup>). Between two possible sampling methods, sub-sampling and reference-sampling, the latter provides a relatively wide locking range, as the slower input reference signal is sampled with the faster VCO output signal. However, removal of FDIV makes the PLL not feasible to implement fractional-N operation based on varying divider ratios through random sequence generators, such as a Delta-Sigma-Modulator (DSM). To address the above design challenges, we propose a reference-sampling-based calibration-free fractional-N PLL (RSFPLL) with a phase-interpolator-linked sampling clock generator (PSCG). The proposed RSFPLL achieves fractional-N operations through phase-interpolator (PI)-based multi-phase generation instead of a typical frequency divider or digital-to-time converter (DTC). In addition, to alleviate the power burden arising from VCO-rated sampling, a flexible mask window generation method has been used that only passes a few sampling clocks near the point of interest. The prototype PLL system is designed with a 65 nm CMOS process with a chip size of 0.42 mm<sup>2</sup>. It achieves 322 fs rms jitter, −240.7 dB figure-of-merit (FoM), and −44.06 dBc fractional spurs with 8.17 mW power consumption. |
| first_indexed | 2024-03-10T06:13:55Z |
| format | Article |
| id | doaj.art-fe02c73a5b254053bb71dcd92f069633 |
| institution | Directory Open Access Journal |
| issn | 1424-8220 |
| language | English |
| last_indexed | 2024-03-10T06:13:55Z |
| publishDate | 2021-10-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Sensors |
| spelling | doaj.art-fe02c73a5b254053bb71dcd92f0696332023-11-22T19:58:03ZengMDPI AGSensors1424-82202021-10-012120682410.3390/s21206824A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock GeneratorJae-Soub Han0Tae-Hyeok Eom1Seong-Wook Choi2Kiho Seong3Dong-Hyun Yoon4Tony Tae-Hyong Kim5Kwang-Hyun Baek6Yong Shim7School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06974, KoreaSamsung Electronics, Hwaseong 18448, KoreaSchool of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06974, KoreaSchool of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06974, KoreaSchool of Electrical and Electronics Engineering, Nanyang Technological University, Singapore 639798, SingaporeSchool of Electrical and Electronics Engineering, Nanyang Technological University, Singapore 639798, SingaporeSchool of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06974, KoreaSchool of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06974, KoreaSampling-based PLLs have become a new research trend due to the possibility of removing the frequency divider (FDIV) from the feedback path, where the FDIV increases the contribution of in-band noise by the factor of dividing ratio square (N<sup>2</sup>). Between two possible sampling methods, sub-sampling and reference-sampling, the latter provides a relatively wide locking range, as the slower input reference signal is sampled with the faster VCO output signal. However, removal of FDIV makes the PLL not feasible to implement fractional-N operation based on varying divider ratios through random sequence generators, such as a Delta-Sigma-Modulator (DSM). To address the above design challenges, we propose a reference-sampling-based calibration-free fractional-N PLL (RSFPLL) with a phase-interpolator-linked sampling clock generator (PSCG). The proposed RSFPLL achieves fractional-N operations through phase-interpolator (PI)-based multi-phase generation instead of a typical frequency divider or digital-to-time converter (DTC). In addition, to alleviate the power burden arising from VCO-rated sampling, a flexible mask window generation method has been used that only passes a few sampling clocks near the point of interest. The prototype PLL system is designed with a 65 nm CMOS process with a chip size of 0.42 mm<sup>2</sup>. It achieves 322 fs rms jitter, −240.7 dB figure-of-merit (FoM), and −44.06 dBc fractional spurs with 8.17 mW power consumption.https://www.mdpi.com/1424-8220/21/20/6824calibration-freefractional-Nfrequency synthesizerlow-phase noiselow powerreference-sampling PLL |
| spellingShingle | Jae-Soub Han Tae-Hyeok Eom Seong-Wook Choi Kiho Seong Dong-Hyun Yoon Tony Tae-Hyong Kim Kwang-Hyun Baek Yong Shim A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator Sensors calibration-free fractional-N frequency synthesizer low-phase noise low power reference-sampling PLL |
| title | A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator |
| title_full | A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator |
| title_fullStr | A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator |
| title_full_unstemmed | A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator |
| title_short | A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator |
| title_sort | reference sampling based calibration free fractional n pll with a pi linked sampling clock generator |
| topic | calibration-free fractional-N frequency synthesizer low-phase noise low power reference-sampling PLL |
| url | https://www.mdpi.com/1424-8220/21/20/6824 |
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