A Size, Weight, Power, and Cost-Efficient 32-Channel Time to Digital Converter Using a Novel Wave Union Method

A Size, Weight, Power, and Cost-Efficient 32-Channel Time to Digital Converter Using a Novel Wave Union Method

We present a Tapped Delay Line (TDL)-based Time to Digital Converter (TDC) using Wave Union type A (WU-A) architecture for applications that require high-precision time interval measurements with low size, weight, power, and cost (SWaP-C) requirements. The proposed TDC is implemented on a low-cost F...

Full description

Bibliographic Details
Main Authors:	Saleh M. Alshahry, Awwad H. Alshehry, Abdullah K. Alhazmi, Vamsy P. Chodavarapu
Format:	Article
Language:	English
Published:	MDPI AG 2023-07-01
Series:	Sensors
Subjects:	time to digital converter (TDC) field programmable gate array (FPGA) wave union tapped delay line (TDL)
Online Access:	https://www.mdpi.com/1424-8220/23/14/6621

Similar Items

A Study on the Effect of Temperature Variations on FPGA-Based Multi-Channel Time-to-Digital Converters
by: Awwad H. Alshehry, et al.
Published: (2023-09-01)

5.7 ps Resolution Time-to-Digital Converter Implementation Using Routing Path Delays
by: Roza Teklehaimanot Siecha, et al.
Published: (2023-08-01)

Linearity improvement of UltraScale+ FPGA-based time-to-digital converter
by: Jaewon Kim, et al.
Published: (2023-02-01)

Relative Jitter Measurement Methodology and Comparison of Clocking Resources Jitter in Artix 7 FPGA
by: Andrzej A. Wojciechowski, et al.
Published: (2023-10-01)

A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA
by: Mojtaba Parsakordasiabi, et al.
Published: (2021-01-01)

Bubble-Proof Algorithm for Wave Union TDCs
by: Paweł Kwiatkowski, et al.
Published: (2021-12-01)

Optimization of a Wideband Tapped-Delay Line Array Antenna
by: N. Noori
Published: (2014-06-01)

A Low Temperature Coefficient Time-to-Digital Converter with 1.3 ps Resolution Implemented in a 28 nm FPGA
by: Xiangyu Mao, et al.
Published: (2022-03-01)

A 1-ps Bin Size 4.87-ps Resolution FPGA Time-to-Digital Converter Based on Phase Wrapping Sorting and Selection
by: Poki Chen, et al.
Published: (2022-01-01)

New High-Rate Timestamp Management with Real-Time Configurable Virtual Delay and Dead Time for FPGA-Based Time-to-Digital Converters
by: Fabio Garzetti, et al.
Published: (2024-03-01)

An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction
by: Zhipeng Song, et al.
Published: (2020-04-01)

A 19 ps Precision and 170 M Samples/s Time-to-Digital Converter Implemented in FPGA with Online Calibration
by: Mengdi Zhang, et al.
Published: (2022-04-01)

Two-Stage Clock-Free Time-to-Digital Converter Based on Vernier and Tapped Delay Lines in FPGA Device
by: Ryszard Szplet, et al.
Published: (2021-09-01)

62.5 ps LSB resolution multiphase clock Time to Digital Converter (TDC) implemented on FPGA
by: Mahantesh Mattada, et al.
Published: (2022-09-01)

Assessment of the Bundle SNSPD Plus FPGA-Based TDC for High-Performance Time Measurements
by: Fabio Garzetti, et al.
Published: (2022-01-01)

A 0.6 V, 1.74 ps resolution capacitively boosted time-to-digital converter in 180 nm CMOS
by: Palaniappan, Arjun Ramaswami, et al.
Published: (2021)

Digital Integration of LiDAR System Implemented in a Low-Cost FPGA
by: Jiajian Huang, et al.
Published: (2022-06-01)

Dual-Mode FPGA-Based Triple-TDC With Real-Time Calibration and a Triple Modular Redundancy Scheme
by: Yuan-Ho Chen
Published: (2020-04-01)

Multi-directional matrix converter for low power application using field-programmable gate array
by: Toosi, Saman
Published: (2015)

Design and implementation of real-time simulation module for non-isolated bidirectional half-bridge DC–DC converter
by: Mingda Zhu, et al.
Published: (2022-11-01)

Sigma-delta analog to digital converter on field programmable gate array
by: Hamadani, Maral Faghani
Published: (2015)

Dual-sampling sigma-delta analog-to-digital converter implementation in field-programmable gate array
by: Noor Shah, Mohd Syahril
Published: (2013)

A Digital Emulator Design for the Swimming Rhythmic Pattern Generator of a Lamprey
by: Nimet Korkmaz
Published: (2024-01-01)

Phase Difference Measurement Method Based on Progressive Phase Shift
by: Min Zhang, et al.
Published: (2018-06-01)

DESARROLLO DE UN SISTEMA PARA EL CONTEO DE MÚLTIPLES SEÑALES ENCOINCIDENCIA BASADO EN TECNOLOGÍA FPGA
by: M. Bolaños, et al.
Published: (2023-03-01)

Design of Portable Quadrupole Mass Spectrometry Control System Based on FPGA
by: GE Wei-min, et al.
Published: (2023-01-01)

Current-controller PWM using FPGA device /
by: 450635 Khoh, Choon Huat
Published: (2002)

Minimization of Network Induced Jitter Impact on FPGA-Based Control Systems for Power Electronics through Forward Error Correction
by: Valentina Bianchi, et al.
Published: (2020-02-01)

FPGA-Based Degradation and Reliability Monitor for Underground Cables
by: Unai Garro, et al.
Published: (2019-04-01)

A Digital Realization of Neuroglial Interaction Model and Its Network Structure
by: Mahsasadat Seyedbarhagh, et al.
Published: (2022-01-01)

Architecture Design of 2-D Discrete Wavelet Transformation Algorithm using Field Programmable Gate Array (FPGA)
by: Maha Hasso, et al.
Published: (2014-07-01)

A Linked List-Based Algorithm for Blob Detection on Embedded Vision-Based Sensors
by: Ricardo Acevedo-Avila, et al.
Published: (2016-05-01)

PAU/RAD: Design and Preliminary Calibration Results of a New L-Band Pseudo-Correlation Radiometer Concept
by: Enric Valencia, et al.
Published: (2008-07-01)

FPGA based delta-sigma converter with interpolation filter /
by: 426491 Chan, Kwan Chien
Published: (2003)

Designing with FPGAs and CPLDs /
by: 240588 Zeidman, Bob
Published: (2002)

Shortest path processor using FPGA /
by: 259595 Rizal Kasyrno Ghazali
Published: (1999)

Development of software interface for shortest path processor [microfilm] /
by: Alagendra Prakash Jayaraman
Published: (2001)

Designing with FPGAs and CPLDs /
by: 378537 Jenkins, Jesse H.
Published: (1994)

Development of software interface for shortest path processor /
by: 238780 Alagendra Prakash Jayaraman
Published: (2001)

Implementation of ether interface for nios processor /
by: 372855 Edwin Edward
Published: (2006)