Design and Implementation of an N-type Integer Phase-locked Loop with Low Phase Noise and Two Output Frequencies at 1 and 4 GHz
This article presents development and implementation of an integer N-type Phase Locked Loop (PLL) module with two output frequencies of 1 and 4 GHz, each having a phase noise better than -110dBC/Hz@10k. The structure has 0 and 10dBm power levels at 1 and 4GHz output frequencies, respectively. Having...
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| Format: | Article |
| Language: | English |
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University of Sistan and Baluchestan
2024-03-01
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| Series: | International Journal of Industrial Electronics, Control and Optimization |
| Subjects: | |
| Online Access: | https://ieco.usb.ac.ir/article_8174_e158d6be2deb0e3e8541c5edc21fed58.pdf |
| _version_ | 1797247659653726208 |
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| author | Hamid Kazemi Karyani Esmaeil Najafiaghdam |
| author_facet | Hamid Kazemi Karyani Esmaeil Najafiaghdam |
| author_sort | Hamid Kazemi Karyani |
| collection | DOAJ |
| description | This article presents development and implementation of an integer N-type Phase Locked Loop (PLL) module with two output frequencies of 1 and 4 GHz, each having a phase noise better than -110dBC/Hz@10k. The structure has 0 and 10dBm power levels at 1 and 4GHz output frequencies, respectively. Having two different outputs of 1 and 4 GHz at once, in addition to the 1.1 and 4.4GHz realized by the capability included in this design in which two additional outputs can be achieved by using the pins A0 to A4 and altering their status, makes this structure a good candidate for mass production. A two-step frequency division is employed in this work. The first step is realized using the frequency divider of order 4, and the second step is implemented inside the HMC440 IC, including a PFD and a counter. Compared to typical methods, this method presents a clean output by suppressing the spurs meant to be manifested using a single-step frequency division. This PLL is constructed in discrete and modular modes and employed in transceivers’ up-converter and down-converter blocks, Satellite communications, Cable TV links (CATV), Local Area Networks (LAN), Global Positioning Systems (GPS), test equipment, digital radios, military and commercial communications. For a specific example, the 4GHz frequency is used to up-converte or down-converte the received signals, and the 1-GHz frequency is usually used for the synthesizer module clock frequency. Advanced Design System (ADS) was used in the design, and OrCAD was used in the schematic design of the PLL module. |
| first_indexed | 2024-04-24T20:02:13Z |
| format | Article |
| id | doaj.art-ff4ee661b446461295cb3513c673b35f |
| institution | Directory Open Access Journal |
| issn | 2645-3517 2645-3568 |
| language | English |
| last_indexed | 2024-04-24T20:02:13Z |
| publishDate | 2024-03-01 |
| publisher | University of Sistan and Baluchestan |
| record_format | Article |
| series | International Journal of Industrial Electronics, Control and Optimization |
| spelling | doaj.art-ff4ee661b446461295cb3513c673b35f2024-03-24T07:57:00ZengUniversity of Sistan and BaluchestanInternational Journal of Industrial Electronics, Control and Optimization2645-35172645-35682024-03-0171293910.22111/ieco.2024.46858.15058174Design and Implementation of an N-type Integer Phase-locked Loop with Low Phase Noise and Two Output Frequencies at 1 and 4 GHzHamid Kazemi Karyani0Esmaeil Najafiaghdam1Department of Electrical Engineering, Sahand University of Technology, Tabriz, IranDepartment of Electrical Engineering, Sahand University of Technology, Tabriz, IranThis article presents development and implementation of an integer N-type Phase Locked Loop (PLL) module with two output frequencies of 1 and 4 GHz, each having a phase noise better than -110dBC/Hz@10k. The structure has 0 and 10dBm power levels at 1 and 4GHz output frequencies, respectively. Having two different outputs of 1 and 4 GHz at once, in addition to the 1.1 and 4.4GHz realized by the capability included in this design in which two additional outputs can be achieved by using the pins A0 to A4 and altering their status, makes this structure a good candidate for mass production. A two-step frequency division is employed in this work. The first step is realized using the frequency divider of order 4, and the second step is implemented inside the HMC440 IC, including a PFD and a counter. Compared to typical methods, this method presents a clean output by suppressing the spurs meant to be manifested using a single-step frequency division. This PLL is constructed in discrete and modular modes and employed in transceivers’ up-converter and down-converter blocks, Satellite communications, Cable TV links (CATV), Local Area Networks (LAN), Global Positioning Systems (GPS), test equipment, digital radios, military and commercial communications. For a specific example, the 4GHz frequency is used to up-converte or down-converte the received signals, and the 1-GHz frequency is usually used for the synthesizer module clock frequency. Advanced Design System (ADS) was used in the design, and OrCAD was used in the schematic design of the PLL module.https://ieco.usb.ac.ir/article_8174_e158d6be2deb0e3e8541c5edc21fed58.pdfphase lock loopphase noiselow phase noisespur |
| spellingShingle | Hamid Kazemi Karyani Esmaeil Najafiaghdam Design and Implementation of an N-type Integer Phase-locked Loop with Low Phase Noise and Two Output Frequencies at 1 and 4 GHz International Journal of Industrial Electronics, Control and Optimization phase lock loop phase noise low phase noise spur |
| title | Design and Implementation of an N-type Integer Phase-locked Loop with Low Phase Noise and Two Output Frequencies at 1 and 4 GHz |
| title_full | Design and Implementation of an N-type Integer Phase-locked Loop with Low Phase Noise and Two Output Frequencies at 1 and 4 GHz |
| title_fullStr | Design and Implementation of an N-type Integer Phase-locked Loop with Low Phase Noise and Two Output Frequencies at 1 and 4 GHz |
| title_full_unstemmed | Design and Implementation of an N-type Integer Phase-locked Loop with Low Phase Noise and Two Output Frequencies at 1 and 4 GHz |
| title_short | Design and Implementation of an N-type Integer Phase-locked Loop with Low Phase Noise and Two Output Frequencies at 1 and 4 GHz |
| title_sort | design and implementation of an n type integer phase locked loop with low phase noise and two output frequencies at 1 and 4 ghz |
| topic | phase lock loop phase noise low phase noise spur |
| url | https://ieco.usb.ac.ir/article_8174_e158d6be2deb0e3e8541c5edc21fed58.pdf |
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