Design and Implementation of an N-type Integer Phase-locked Loop with Low Phase Noise and Two Output Frequencies at 1 and 4 GHz
This article presents development and implementation of an integer N-type Phase Locked Loop (PLL) module with two output frequencies of 1 and 4 GHz, each having a phase noise better than -110dBC/Hz@10k. The structure has 0 and 10dBm power levels at 1 and 4GHz output frequencies, respectively. Having...
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
University of Sistan and Baluchestan
2024-03-01
|
| Series: | International Journal of Industrial Electronics, Control and Optimization |
| Subjects: | |
| Online Access: | https://ieco.usb.ac.ir/article_8174_e158d6be2deb0e3e8541c5edc21fed58.pdf |