| Summary: | Negative capacitance field effect transistors (NCFETs) are modeled in this study, with an emphasis on junction design, implications of complementary logic, and device <inline-formula> <tex-math notation="LaTeX">$V_{t}$ </tex-math></inline-formula> menu enablement. Contrary to conventional MOSFET design, increased junction overlap is beneficial to NCFETs, provided the remnant polarization (<inline-formula> <tex-math notation="LaTeX">$P_{r}$ </tex-math></inline-formula>) is high enough. Combining broad junctions with complementary capacitance matching (CCM) in MFMIS (metal/ferroelectric/metal/insulator/semiconductor) NCFETs, it is shown that super-steep and non-hysteretic switching are not mutually exclusive, and that it is theoretically possible to achieve non-hysteretic sub-5 mV/dec <italic>SS</italic> over >6 decades. In a CMOS circuit, due to CCM, low- <inline-formula> <tex-math notation="LaTeX">$V_{t}$ </tex-math></inline-formula> pairs provide steeper subthreshold swing (<italic>SS</italic>) than high- <inline-formula> <tex-math notation="LaTeX">$V_{t}$ </tex-math></inline-formula> pairs. Transient power/performance is also modeled, and it is shown that a DC-optimal NCFET design, employing broad junctions, CCM, and a low- <inline-formula> <tex-math notation="LaTeX">$V_{t}$ </tex-math></inline-formula> NFET/PFET pair, does not translate to improved AC power/performance in unloaded circuits compared to a conventional FET reference. It is also shown that the same non-hysteretic DC design point is hysteretic in AC and may also lead to full polarization switching at higher voltages. Thus, a usable voltage window for AC NCFET operation forces a retreat from the DC-optimal design point.
|
|---|