Junction Design and Complementary Capacitance Matching for NCFET CMOS Logic
Negative capacitance field effect transistors (NCFETs) are modeled in this study, with an emphasis on junction design, implications of complementary logic, and device <inline-formula> <tex-math notation="LaTeX">$V_{t}$ </tex-math></inline-formula> menu enablement. C...
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| Format: | Article |
| Language: | English |
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IEEE
2021-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9478918/ |
| _version_ | 1818922000142303232 |
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| author | Reinaldo A. Vega Takashi Ando Timothy M. Philip |
| author_facet | Reinaldo A. Vega Takashi Ando Timothy M. Philip |
| author_sort | Reinaldo A. Vega |
| collection | DOAJ |
| description | Negative capacitance field effect transistors (NCFETs) are modeled in this study, with an emphasis on junction design, implications of complementary logic, and device <inline-formula> <tex-math notation="LaTeX">$V_{t}$ </tex-math></inline-formula> menu enablement. Contrary to conventional MOSFET design, increased junction overlap is beneficial to NCFETs, provided the remnant polarization (<inline-formula> <tex-math notation="LaTeX">$P_{r}$ </tex-math></inline-formula>) is high enough. Combining broad junctions with complementary capacitance matching (CCM) in MFMIS (metal/ferroelectric/metal/insulator/semiconductor) NCFETs, it is shown that super-steep and non-hysteretic switching are not mutually exclusive, and that it is theoretically possible to achieve non-hysteretic sub-5 mV/dec <italic>SS</italic> over >6 decades. In a CMOS circuit, due to CCM, low- <inline-formula> <tex-math notation="LaTeX">$V_{t}$ </tex-math></inline-formula> pairs provide steeper subthreshold swing (<italic>SS</italic>) than high- <inline-formula> <tex-math notation="LaTeX">$V_{t}$ </tex-math></inline-formula> pairs. Transient power/performance is also modeled, and it is shown that a DC-optimal NCFET design, employing broad junctions, CCM, and a low- <inline-formula> <tex-math notation="LaTeX">$V_{t}$ </tex-math></inline-formula> NFET/PFET pair, does not translate to improved AC power/performance in unloaded circuits compared to a conventional FET reference. It is also shown that the same non-hysteretic DC design point is hysteretic in AC and may also lead to full polarization switching at higher voltages. Thus, a usable voltage window for AC NCFET operation forces a retreat from the DC-optimal design point. |
| first_indexed | 2024-12-20T01:46:35Z |
| format | Article |
| id | doaj.art-ff5ba9ee93c848269683df9bad3f9726 |
| institution | Directory Open Access Journal |
| issn | 2168-6734 |
| language | English |
| last_indexed | 2024-12-20T01:46:35Z |
| publishDate | 2021-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj.art-ff5ba9ee93c848269683df9bad3f97262022-12-21T19:57:45ZengIEEEIEEE Journal of the Electron Devices Society2168-67342021-01-01969170310.1109/JEDS.2021.30959239478918Junction Design and Complementary Capacitance Matching for NCFET CMOS LogicReinaldo A. Vega0https://orcid.org/0000-0001-6407-0081Takashi Ando1https://orcid.org/0000-0002-1097-818XTimothy M. Philip2https://orcid.org/0000-0001-6522-0563IBM Research, Albany Nanotech, Albany, NY, USAIBM Research, IBM T.J. Watson Research Center, Yorktown Heights, NY, USAIBM Research, Albany Nanotech, Albany, NY, USANegative capacitance field effect transistors (NCFETs) are modeled in this study, with an emphasis on junction design, implications of complementary logic, and device <inline-formula> <tex-math notation="LaTeX">$V_{t}$ </tex-math></inline-formula> menu enablement. Contrary to conventional MOSFET design, increased junction overlap is beneficial to NCFETs, provided the remnant polarization (<inline-formula> <tex-math notation="LaTeX">$P_{r}$ </tex-math></inline-formula>) is high enough. Combining broad junctions with complementary capacitance matching (CCM) in MFMIS (metal/ferroelectric/metal/insulator/semiconductor) NCFETs, it is shown that super-steep and non-hysteretic switching are not mutually exclusive, and that it is theoretically possible to achieve non-hysteretic sub-5 mV/dec <italic>SS</italic> over >6 decades. In a CMOS circuit, due to CCM, low- <inline-formula> <tex-math notation="LaTeX">$V_{t}$ </tex-math></inline-formula> pairs provide steeper subthreshold swing (<italic>SS</italic>) than high- <inline-formula> <tex-math notation="LaTeX">$V_{t}$ </tex-math></inline-formula> pairs. Transient power/performance is also modeled, and it is shown that a DC-optimal NCFET design, employing broad junctions, CCM, and a low- <inline-formula> <tex-math notation="LaTeX">$V_{t}$ </tex-math></inline-formula> NFET/PFET pair, does not translate to improved AC power/performance in unloaded circuits compared to a conventional FET reference. It is also shown that the same non-hysteretic DC design point is hysteretic in AC and may also lead to full polarization switching at higher voltages. Thus, a usable voltage window for AC NCFET operation forces a retreat from the DC-optimal design point.https://ieeexplore.ieee.org/document/9478918/Ferroelectricnegative capacitancemodelingTCADcapacitance matchingjunction design |
| spellingShingle | Reinaldo A. Vega Takashi Ando Timothy M. Philip Junction Design and Complementary Capacitance Matching for NCFET CMOS Logic IEEE Journal of the Electron Devices Society Ferroelectric negative capacitance modeling TCAD capacitance matching junction design |
| title | Junction Design and Complementary Capacitance Matching for NCFET CMOS Logic |
| title_full | Junction Design and Complementary Capacitance Matching for NCFET CMOS Logic |
| title_fullStr | Junction Design and Complementary Capacitance Matching for NCFET CMOS Logic |
| title_full_unstemmed | Junction Design and Complementary Capacitance Matching for NCFET CMOS Logic |
| title_short | Junction Design and Complementary Capacitance Matching for NCFET CMOS Logic |
| title_sort | junction design and complementary capacitance matching for ncfet cmos logic |
| topic | Ferroelectric negative capacitance modeling TCAD capacitance matching junction design |
| url | https://ieeexplore.ieee.org/document/9478918/ |
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