Floating Fin Shaped Stacked Nanosheet MOSFET for Low Power Logic Application - Munhyeon Kim; Sihyun Kim; Kitae Lee; Jong-Ho Lee; Byung-Gook Park; Daewoong Kwon (IEEE Journal of the Electron Devices Society, 2023)
In this paper, floating fin structured vertically stacked nanosheet gate-all-around (GAA) metal oxide semiconductor field-effect transistor (FNS) is proposed for low power logic device applications. To verify the electrical performance of the proposed device, three-dimensional (3-D) technology computer-aided design (TCAD) device/circuit simulations are performed with calibrated device model parameters. As a result, it is found that gate propagation delay $({τ }_{ delay})$ and dynamic power $(P_{ dyn})$ are improved by 8% and 19%. respectively as compared to conventional vertically stacked lateral nanosheet (LNS). Through the rigorous analysis on the resistance and capacitance components of FNS and LNS, it is clearly revealed that the ${τ }_{ delay}$ and $P_{ dyn}$ are improved at the same $P_{ dyn}$ (50 $μ \text{W}$ ) and ${τ }_{ delay}$ (187 GHz) by the reduced effective capacitance which results from the diminished gate-to-sorece/drain overlap area. Based on the TCAD simulation studies, it is expected that the FNS is suitable for next generation logic digital applications.