Decoder Hardware Architecture for HEVC
This chapter provides an overview of the design challenges faced in the implementation of hardware HEVC decoders. These challenges can be attributed to the larger and diverse coding block sizes and transform sizes, the larger interpolation filter for motion compensation, the increased number of step...
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| Format: | Article |
| Language: | en_US |
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Springer-Verlag
2015
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| Online Access: | http://hdl.handle.net/1721.1/100391 https://orcid.org/0000-0002-8725-9669 https://orcid.org/0000-0002-5977-2748 https://orcid.org/0000-0003-4841-3990 https://orcid.org/0000-0003-1872-1976 |
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| author | Tikekar, Mehul Huang, Chao-Tsung Sze, Vivienne Juvekar, Chiraag Shashikant Chandrakasan, Anantha P. |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Tikekar, Mehul Huang, Chao-Tsung Sze, Vivienne Juvekar, Chiraag Shashikant Chandrakasan, Anantha P. |
| author_sort | Tikekar, Mehul |
| collection | MIT |
| description | This chapter provides an overview of the design challenges faced in the implementation of hardware HEVC decoders. These challenges can be attributed to the larger and diverse coding block sizes and transform sizes, the larger interpolation filter for motion compensation, the increased number of steps in intra prediction and the introduction of a new in-loop filter. Several solutions to address these implementation challenges are discussed. As a reference, results for an HEVC decoder test chip are also presented. |
| first_indexed | 2024-09-23T11:01:13Z |
| format | Article |
| id | mit-1721.1/100391 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T11:01:13Z |
| publishDate | 2015 |
| publisher | Springer-Verlag |
| record_format | dspace |
| spelling | mit-1721.1/1003912022-09-27T16:35:55Z Decoder Hardware Architecture for HEVC Tikekar, Mehul Huang, Chao-Tsung Sze, Vivienne Juvekar, Chiraag Shashikant Chandrakasan, Anantha P. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Sze, Vivienne Tikekar, Mehul Sze, Vivienne Juvekar, Chiraag Shashikant Chandrakasan, Anantha P. This chapter provides an overview of the design challenges faced in the implementation of hardware HEVC decoders. These challenges can be attributed to the larger and diverse coding block sizes and transform sizes, the larger interpolation filter for motion compensation, the increased number of steps in intra prediction and the introduction of a new in-loop filter. Several solutions to address these implementation challenges are discussed. As a reference, results for an HEVC decoder test chip are also presented. Texas Instruments Incorporated 2015-12-16T16:47:01Z 2015-12-16T16:47:01Z 2014 Article http://purl.org/eprint/type/BookItem 978-3-319-06894-7 978-3-319-06895-4 1558-9412 http://hdl.handle.net/1721.1/100391 Tikekar, Mehul, Chao-Tsung Huang, Chiraag Juvekar, Vivienne Sze, and Anantha Chandrakasan. “Decoder Hardware Architecture for HEVC.” High Efficiency Video Coding (HEVC) (2014): 303–341. https://orcid.org/0000-0002-8725-9669 https://orcid.org/0000-0002-5977-2748 https://orcid.org/0000-0003-4841-3990 https://orcid.org/0000-0003-1872-1976 en_US http://dx.doi.org/10.1007/978-3-319-06895-4_10 High Efficiency Video Coding (HEVC) Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf Springer-Verlag Sze |
| spellingShingle | Tikekar, Mehul Huang, Chao-Tsung Sze, Vivienne Juvekar, Chiraag Shashikant Chandrakasan, Anantha P. Decoder Hardware Architecture for HEVC |
| title | Decoder Hardware Architecture for HEVC |
| title_full | Decoder Hardware Architecture for HEVC |
| title_fullStr | Decoder Hardware Architecture for HEVC |
| title_full_unstemmed | Decoder Hardware Architecture for HEVC |
| title_short | Decoder Hardware Architecture for HEVC |
| title_sort | decoder hardware architecture for hevc |
| url | http://hdl.handle.net/1721.1/100391 https://orcid.org/0000-0002-8725-9669 https://orcid.org/0000-0002-5977-2748 https://orcid.org/0000-0003-4841-3990 https://orcid.org/0000-0003-1872-1976 |
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