Decoder Hardware Architecture for HEVC
This chapter provides an overview of the design challenges faced in the implementation of hardware HEVC decoders. These challenges can be attributed to the larger and diverse coding block sizes and transform sizes, the larger interpolation filter for motion compensation, the increased number of step...
| Main Authors: | , , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | en_US |
| Published: |
Springer-Verlag
2015
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| Online Access: | http://hdl.handle.net/1721.1/100391 https://orcid.org/0000-0002-8725-9669 https://orcid.org/0000-0002-5977-2748 https://orcid.org/0000-0003-4841-3990 https://orcid.org/0000-0003-1872-1976 |