Reduced Hardware NOrec: A Safe and Scalable Hybrid Transactional Memory
Because of hardware TM limitations, software fallbacks are the only way to make TM algorithms guarantee progress. Nevertheless, all known software fallbacks to date, from simple locks to sophisticated versions of the NOrec Hybrid TM algorithm, have either limited scalability or weakened semantics. W...
| Main Authors: | , |
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| Format: | Article |
| Language: | en_US |
| Published: |
Association for Computing Machinery (ACM)
2016
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| Online Access: | http://hdl.handle.net/1721.1/101057 https://orcid.org/0000-0003-4235-0036 https://orcid.org/0000-0002-4552-2414 |