SC²EPTON : high-performance and scalable, low-power and intelligent, ordered Mesh on-chip network
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2016
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| Online Access: | http://hdl.handle.net/1721.1/101569 |
| _version_ | 1826194648167612416 |
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| author | Daya, Bhavya Kishor |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Daya, Bhavya Kishor |
| author_sort | Daya, Bhavya Kishor |
| collection | MIT |
| description | Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015. |
| first_indexed | 2024-09-23T09:59:48Z |
| format | Thesis |
| id | mit-1721.1/101569 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T09:59:48Z |
| publishDate | 2016 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/1015692019-04-11T01:07:32Z SC²EPTON : high-performance and scalable, low-power and intelligent, ordered Mesh on-chip network High-performance and scalable, low-power and intelligent, ordered Mesh on-chip network Daya, Bhavya Kishor Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015. Cataloged from PDF version of thesis. Includes bibliographical references (pages 156-162). Over the last few decades, hindrances to performance and voltage scaling led to a shift from uniprocessors to multicore processors, to the point where the on-chip interconnect plays a larger role in achieving the desired performance and power goals. Shared memory multicores are subject to data sharing concerns as each processor computes on data locally, and needs to be aware of accesses by other cores. Hardware cache coherence addresses the problem, and provides superior performance to software-implemented coherence, but is limited within practical constraints, i.e. area, power, timing. Scaling coherence to higher core counts, presents challenges of unscalable storage, high power consumption, and increased on-chip network traffic. SC²EPTON targets the three challenges with three on-chip networks - SCORPIO, SCEPTER, SB² . SCORPIO addresses the unscalable storage plaguing directory-based coherence, with a 36-core chip prototype showcasing a novel distributed global ordering mechanism to support snoopy coherence over scalable mesh networks. Although the downsides of a directory are averted, the network itself consumes a significant fraction of the total chip power, of which the router buffer power dominates. SCEPTER is a bufferless mesh NoC that reduces the network power consumption, and achieves high performance by intelligently prioritizing, routing, and throttling flits to maximize opportunities to bypass on dynamically set, virtual single-cycle express paths. For unicast communication, SCEPTER performs on-par with state-of-the-art buffered networks, however broadcasts exacerbate the link contention at bisection and ejection links, limiting performance gains. SB² addresses the broadcast traffic in bufferless NoCs with a TDM-based embedded ring architecture that dynamically determines ring access, allows multiple sources simultaneous contention-free access, and sets the control path locally at each node within the same cycle. The three NoCs contribute key elements to the SC²EPTON architecture, resulting in a low-power and high-performance bufferless snoopy coherent mesh network. by Bhavya Kishor Daya. Ph. D. 2016-03-03T21:09:36Z 2016-03-03T21:09:36Z 2015 2015 Thesis http://hdl.handle.net/1721.1/101569 940571756 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 162 pages application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Daya, Bhavya Kishor SC²EPTON : high-performance and scalable, low-power and intelligent, ordered Mesh on-chip network |
| title | SC²EPTON : high-performance and scalable, low-power and intelligent, ordered Mesh on-chip network |
| title_full | SC²EPTON : high-performance and scalable, low-power and intelligent, ordered Mesh on-chip network |
| title_fullStr | SC²EPTON : high-performance and scalable, low-power and intelligent, ordered Mesh on-chip network |
| title_full_unstemmed | SC²EPTON : high-performance and scalable, low-power and intelligent, ordered Mesh on-chip network |
| title_short | SC²EPTON : high-performance and scalable, low-power and intelligent, ordered Mesh on-chip network |
| title_sort | sc²epton high performance and scalable low power and intelligent ordered mesh on chip network |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/101569 |
| work_keys_str_mv | AT dayabhavyakishor sc2eptonhighperformanceandscalablelowpowerandintelligentorderedmeshonchipnetwork AT dayabhavyakishor highperformanceandscalablelowpowerandintelligentorderedmeshonchipnetwork |