Design of on-chip monitoring circuits for clock delay and temperature

Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.

Bibliographic Details
Main Author: Kakuru, George Bamuturaki
Other Authors: Charles G. Sodini, Jeremy Walker, and Andrew Lewine.
Format: Thesis
Language:eng
Published: Massachusetts Institute of Technology 2016
Subjects:
Online Access:http://hdl.handle.net/1721.1/105997
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author Kakuru, George Bamuturaki
author2 Charles G. Sodini, Jeremy Walker, and Andrew Lewine.
author_facet Charles G. Sodini, Jeremy Walker, and Andrew Lewine.
Kakuru, George Bamuturaki
author_sort Kakuru, George Bamuturaki
collection MIT
description Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.
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spelling mit-1721.1/1059972019-04-12T17:18:44Z Design of on-chip monitoring circuits for clock delay and temperature Kakuru, George Bamuturaki Charles G. Sodini, Jeremy Walker, and Andrew Lewine. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016. This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. Cataloged from student-submitted PDF version of thesis. Includes bibliographical references (pages 81-82). As devices continue to scale, Process, Voltage and Temperature (PVT) variations tend to have a bigger impact on circuit performance. The ability to measure this impact provides essential knowledge about the circuit's current performance and opens the door to compensation techniques. Off-chip measurement circuits are usually of limited bandwidth and load the measured circuit, thus affecting the measurement result. Onchip circuits on the other hand have the potential for high bandwidth and, if designed well, have small area and can be incorporated into different parts of the chip. For this project a delay and temperature measurement circuit is designed. The delay measurement circuit relies on a method called Code Density Test (CDT), a statistical method which involves counting the number of asynchronous edges that occur within the relative delay of two synchronous clocks. The temperature measurement circuit converts temperature to a delay which can then be measured by the CDT circuit. by George Bamuturaki Kakuru. M. Eng. 2016-12-22T15:17:57Z 2016-12-22T15:17:57Z 2016 2016 Thesis http://hdl.handle.net/1721.1/105997 965798463 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 82 pages application/pdf Massachusetts Institute of Technology
spellingShingle Electrical Engineering and Computer Science.
Kakuru, George Bamuturaki
Design of on-chip monitoring circuits for clock delay and temperature
title Design of on-chip monitoring circuits for clock delay and temperature
title_full Design of on-chip monitoring circuits for clock delay and temperature
title_fullStr Design of on-chip monitoring circuits for clock delay and temperature
title_full_unstemmed Design of on-chip monitoring circuits for clock delay and temperature
title_short Design of on-chip monitoring circuits for clock delay and temperature
title_sort design of on chip monitoring circuits for clock delay and temperature
topic Electrical Engineering and Computer Science.
url http://hdl.handle.net/1721.1/105997
work_keys_str_mv AT kakurugeorgebamuturaki designofonchipmonitoringcircuitsforclockdelayandtemperature