Design of experiments on a semiconductor plasma ashing process : methods and analysis
Thesis: M. Eng. in Advanced Manufacturing and Design, Massachusetts Institute of Technology, Department of Mechanical Engineering, 2016.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2017
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| Online Access: | http://hdl.handle.net/1721.1/107024 |
| _version_ | 1811074428303310848 |
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| author | Nerurkar, Tanay Rahul |
| author2 | Duane S. Boning. |
| author_facet | Duane S. Boning. Nerurkar, Tanay Rahul |
| author_sort | Nerurkar, Tanay Rahul |
| collection | MIT |
| description | Thesis: M. Eng. in Advanced Manufacturing and Design, Massachusetts Institute of Technology, Department of Mechanical Engineering, 2016. |
| first_indexed | 2024-09-23T09:49:19Z |
| format | Thesis |
| id | mit-1721.1/107024 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T09:49:19Z |
| publishDate | 2017 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/1070242019-04-12T15:24:33Z Design of experiments on a semiconductor plasma ashing process : methods and analysis Nerurkar, Tanay Rahul Duane S. Boning. Massachusetts Institute of Technology. Department of Mechanical Engineering. Massachusetts Institute of Technology. Department of Mechanical Engineering. Mechanical Engineering. Thesis: M. Eng. in Advanced Manufacturing and Design, Massachusetts Institute of Technology, Department of Mechanical Engineering, 2016. This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. Cataloged from student-submitted PDF version of thesis. Includes bibliographical references (pages 115-117). Characterizing and controlling process variations in semiconductor manufacturing processes is crucial to ensure the extremely low defect and scrap rates that are needed for semiconductor manufacturing companies to maximize profitability. As semiconductor device critical dimensions become smaller and chips become more complex, and with customers inquiring about process capability metrics to make sure they get the highest quality product, there is a need for chip manufacturers to thoroughly analyze and define their process capabilities. The work in this thesis done in collaboration with Analog Devices Inc., a leading chip manufacturer, shows how the concept of design of experiments (DOE) and statistical regression modeling techniques can be implemented in a practical industrial setting to rigorously understand and mathematically characterize process variations in a semiconductor fabrication process (plasma ashing). New approaches are introduced to Analog Devices Inc. in calculating wafer statistics. Methodologies are developed that will help the company to choose the right experimental designs based on the objective (e.g. accurate prediction of the response variable, process optimization, process robustness, etc.) while taking into account the process, time, and cost constraints. Multiple regression modeling techniques are utilized to analyze the outcomes of the experiment and the results of these techniques are compared to each other in order to choose the right model needed to satisfy the objective. The statistical software JMP is used to tease out subtle implications of the outcomes of the DOE and formulate hypotheses about any anomalies. The DOEs are performed on two Gasonics Aura 3010 machines that carry out the plasma ashing process using the same process parameters in order to highlight not only the similarities but also the differences in the machines which come from factors like the intrinsic build and state of the machines. The findings and results identify opportunities for the development of new process improvement strategies, faster root cause analysis of failures, methods to systematically calibrate new equipment, update standard operating procedures, and opportunities for machine matching. The purpose of this thesis is to serve as a pedagogical document and template for the process engineers at Analog Devices Inc. in the future to perform DOEs on other processes and machines in the fabrication center. by Tanay Rahul Nerurkar. M. Eng. in Advanced Manufacturing and Design 2017-02-22T15:59:28Z 2017-02-22T15:59:28Z 2016 2016 Thesis http://hdl.handle.net/1721.1/107024 971137195 eng MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission. http://dspace.mit.edu/handle/1721.1/7582 117 pages application/pdf Massachusetts Institute of Technology |
| spellingShingle | Mechanical Engineering. Nerurkar, Tanay Rahul Design of experiments on a semiconductor plasma ashing process : methods and analysis |
| title | Design of experiments on a semiconductor plasma ashing process : methods and analysis |
| title_full | Design of experiments on a semiconductor plasma ashing process : methods and analysis |
| title_fullStr | Design of experiments on a semiconductor plasma ashing process : methods and analysis |
| title_full_unstemmed | Design of experiments on a semiconductor plasma ashing process : methods and analysis |
| title_short | Design of experiments on a semiconductor plasma ashing process : methods and analysis |
| title_sort | design of experiments on a semiconductor plasma ashing process methods and analysis |
| topic | Mechanical Engineering. |
| url | http://hdl.handle.net/1721.1/107024 |
| work_keys_str_mv | AT nerurkartanayrahul designofexperimentsonasemiconductorplasmaashingprocessmethodsandanalysis |