Growth of InGaAs-channel transistor layers on large-scale Si wafers for HeteroIntegration with Si CMOS
We report on the growth of In 0.30 Ga 0.70 As channel high-electron mobility transistor (HEMT) epi-layers on a 200 mm silicon wafer by metal organic chemical vapor deposition (MOCVD). The device epi-layers were grown on a silicon substrate by using a ∼ 3 μm thick buffer comprising a Ge layer, a GaAs...
| Main Authors: | , , , , , , , , , , , |
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CS Mantech
2017
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| Online Access: | http://hdl.handle.net/1721.1/111840 https://orcid.org/0000-0002-1891-1959 |
| _version_ | 1811080405359525888 |
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| author | Nguyen, X.S. Yadav, S. Lee, K.H. Kohen, D. Kumar, A. Made, R.I. Gong, X. Lee, K.E. Tan, C.S. Yoon, S.F. Chua, S.J. Fitzgerald, Eugene A |
| author2 | Massachusetts Institute of Technology. Department of Materials Science and Engineering |
| author_facet | Massachusetts Institute of Technology. Department of Materials Science and Engineering Nguyen, X.S. Yadav, S. Lee, K.H. Kohen, D. Kumar, A. Made, R.I. Gong, X. Lee, K.E. Tan, C.S. Yoon, S.F. Chua, S.J. Fitzgerald, Eugene A |
| author_sort | Nguyen, X.S. |
| collection | MIT |
| description | We report on the growth of In 0.30 Ga 0.70 As channel high-electron mobility transistor (HEMT) epi-layers on a 200 mm silicon wafer by metal organic chemical vapor deposition (MOCVD). The device epi-layers were grown on a silicon substrate by using a ∼ 3 μm thick buffer comprising a Ge layer, a GaAs layer and an InAlAs compositionally graded, strain relaxation layer. The achieved epitaxy has a threading dislocation density of (1 - 2) × 10[superscript 7] cm[superscript -2] and a root mean square surface roughness of 6-7 nm. The device active layers include a delta-doped InAlAs bottom barrier, a 15 nm thick InGaAs channel, a 15 nm InGaP top barrier layer and a heavily doped InGaAs contact layer. Long channel MOS-HEMT devices (LG ∼ 20 μm), were fabricated achieving a peak effective electron mobility of ∼ 3700 cm[superscript 2]/V·s. |
| first_indexed | 2024-09-23T11:31:08Z |
| format | Article |
| id | mit-1721.1/111840 |
| institution | Massachusetts Institute of Technology |
| last_indexed | 2024-09-23T11:31:08Z |
| publishDate | 2017 |
| publisher | CS Mantech |
| record_format | dspace |
| spelling | mit-1721.1/1118402022-09-27T20:05:12Z Growth of InGaAs-channel transistor layers on large-scale Si wafers for HeteroIntegration with Si CMOS Nguyen, X.S. Yadav, S. Lee, K.H. Kohen, D. Kumar, A. Made, R.I. Gong, X. Lee, K.E. Tan, C.S. Yoon, S.F. Chua, S.J. Fitzgerald, Eugene A Massachusetts Institute of Technology. Department of Materials Science and Engineering Fitzgerald, Eugene A We report on the growth of In 0.30 Ga 0.70 As channel high-electron mobility transistor (HEMT) epi-layers on a 200 mm silicon wafer by metal organic chemical vapor deposition (MOCVD). The device epi-layers were grown on a silicon substrate by using a ∼ 3 μm thick buffer comprising a Ge layer, a GaAs layer and an InAlAs compositionally graded, strain relaxation layer. The achieved epitaxy has a threading dislocation density of (1 - 2) × 10[superscript 7] cm[superscript -2] and a root mean square surface roughness of 6-7 nm. The device active layers include a delta-doped InAlAs bottom barrier, a 15 nm thick InGaAs channel, a 15 nm InGaP top barrier layer and a heavily doped InGaAs contact layer. Long channel MOS-HEMT devices (LG ∼ 20 μm), were fabricated achieving a peak effective electron mobility of ∼ 3700 cm[superscript 2]/V·s. 2017-10-11T13:31:01Z 2017-10-11T13:31:01Z 2017-05 2017-10-06T13:33:36Z Article http://purl.org/eprint/type/ConferencePaper http://hdl.handle.net/1721.1/111840 Nguyen, X.S. et al. "Growth of InGaAs-channel transistor layers on large-scale Si wafers for HeteroIntegration with Si CMOS." 2017 International Conference on Compound Semiconductor Manufacturing Technology(2017 CS MANTECH Conference), May 22-25 2017, Indian Wells, California, USA, CS Mantech, May 2017 https://orcid.org/0000-0002-1891-1959 http://csmantech2017.conferencespot.org/64646gmi-1.3606545/t008-1.3607215/f008-1.3607216/0889-000037-1.3607220/ap014-1.3607221 2017 International Conference on Compound Semiconductor Manufacturing Technology(2017 CS MANTECH Conference) Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf CS Mantech Other repository |
| spellingShingle | Nguyen, X.S. Yadav, S. Lee, K.H. Kohen, D. Kumar, A. Made, R.I. Gong, X. Lee, K.E. Tan, C.S. Yoon, S.F. Chua, S.J. Fitzgerald, Eugene A Growth of InGaAs-channel transistor layers on large-scale Si wafers for HeteroIntegration with Si CMOS |
| title | Growth of InGaAs-channel transistor layers on large-scale Si wafers for HeteroIntegration with Si CMOS |
| title_full | Growth of InGaAs-channel transistor layers on large-scale Si wafers for HeteroIntegration with Si CMOS |
| title_fullStr | Growth of InGaAs-channel transistor layers on large-scale Si wafers for HeteroIntegration with Si CMOS |
| title_full_unstemmed | Growth of InGaAs-channel transistor layers on large-scale Si wafers for HeteroIntegration with Si CMOS |
| title_short | Growth of InGaAs-channel transistor layers on large-scale Si wafers for HeteroIntegration with Si CMOS |
| title_sort | growth of ingaas channel transistor layers on large scale si wafers for heterointegration with si cmos |
| url | http://hdl.handle.net/1721.1/111840 https://orcid.org/0000-0002-1891-1959 |
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