Optimizing throughput architectures for speculative parallelism
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2017
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| Online Access: | http://hdl.handle.net/1721.1/111930 |
| _version_ | 1811087303250018304 |
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| author | Abeydeera, Maleen Hasanka (Weeraratna Patabendige Maleen Hasanka) |
| author2 | Daniel Sanchez. |
| author_facet | Daniel Sanchez. Abeydeera, Maleen Hasanka (Weeraratna Patabendige Maleen Hasanka) |
| author_sort | Abeydeera, Maleen Hasanka (Weeraratna Patabendige Maleen Hasanka) |
| collection | MIT |
| description | Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017. |
| first_indexed | 2024-09-23T13:43:56Z |
| format | Thesis |
| id | mit-1721.1/111930 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T13:43:56Z |
| publishDate | 2017 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/1119302019-04-11T07:16:00Z Optimizing throughput architectures for speculative parallelism Abeydeera, Maleen Hasanka (Weeraratna Patabendige Maleen Hasanka) Daniel Sanchez. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017. Cataloged from PDF version of thesis. Includes bibliographical references (pages 57-62). Throughput-oriented architectures, like GPUs, use a large number of simple cores and rely on application-level parallelism, using multithreading to keep the cores busy. These architectures work well when parallelism is plentiful but work poorly when its not. Therefore, it is important to combine these techniques with other hardware support for parallelizing challenging applications. Recent work has shown that speculative parallelism is plentiful for a large class of applications that have traditionally been hard to parallelize. However, adding hardware support for speculative parallelism to a throughput-oriented system leads to a severe pathology: aborted work consumes scarce resources and hurts the throughput of useful work. This thesis develops a technique to optimize throughput-oriented architectures for speculative parallelism: tasks should be prioritized according to how speculative they are. This focuses resources on work that is more likely to commit, reducing aborts and using speculation resources more efficiently. We identify two on-chip resources where this prioritization is most likely to help, the core pipeline and the memory controller. First, this thesis presents speculation-aware multithreading (SAM), a simple policy that modifies a multithreaded processor pipeline to prioritize instructions from less speculative tasks. Second, we modify the on-chip memory controller to prioritize requests issued by tasks that are earlier in the conflict resolution order. We evaluate SAM on systems with up to 64 SMT cores. With SAM, 8-threaded in-order cores outperform single-threaded cores by 2.41 x on average, while a speculation-oblivious policy yields a 1.91 x speedup. SAM also reduces wasted work by 43%. Unlike at the core, we find little performance benefit from prioritizing requests at the memory controller. The reason is that speculative execution works as a very effective prefetching mechanism, and most requests, even those from tasks that are ultimately aborted, do end up being useful. by Weeraratna Patabendige Maleen Hasanka Abeydeera. S.M. 2017-10-18T15:10:30Z 2017-10-18T15:10:30Z 2017 2017 Thesis http://hdl.handle.net/1721.1/111930 1005737748 eng MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission. http://dspace.mit.edu/handle/1721.1/7582 62 pages application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Abeydeera, Maleen Hasanka (Weeraratna Patabendige Maleen Hasanka) Optimizing throughput architectures for speculative parallelism |
| title | Optimizing throughput architectures for speculative parallelism |
| title_full | Optimizing throughput architectures for speculative parallelism |
| title_fullStr | Optimizing throughput architectures for speculative parallelism |
| title_full_unstemmed | Optimizing throughput architectures for speculative parallelism |
| title_short | Optimizing throughput architectures for speculative parallelism |
| title_sort | optimizing throughput architectures for speculative parallelism |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/111930 |
| work_keys_str_mv | AT abeydeeramaleenhasankaweeraratnapatabendigemaleenhasanka optimizingthroughputarchitecturesforspeculativeparallelism |