Kwon, W. C., & Peh, L. (2018). Co-design of on-chip caches and networks for scalable shared-memory many-core CMPs. Massachusetts Institute of Technology.
Chicago Style (17th ed.) CitationKwon, Woo Cheol, and Li-Shiuan Peh. Co-design of On-chip Caches and Networks for Scalable Shared-memory Many-core CMPs. Massachusetts Institute of Technology, 2018.
MLA (9th ed.) CitationKwon, Woo Cheol, and Li-Shiuan Peh. Co-design of On-chip Caches and Networks for Scalable Shared-memory Many-core CMPs. Massachusetts Institute of Technology, 2018.
Warning: These citations may not always be 100% accurate.