Co-design of on-chip caches and networks for scalable shared-memory many-core CMPs
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018.
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| Other Authors: | |
| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2018
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| Online Access: | http://hdl.handle.net/1721.1/118084 |
| _version_ | 1826198959346941952 |
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| author | Kwon, Woo Cheol |
| author2 | Li-Shiuan Peh. |
| author_facet | Li-Shiuan Peh. Kwon, Woo Cheol |
| author_sort | Kwon, Woo Cheol |
| collection | MIT |
| description | Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018. |
| first_indexed | 2024-09-23T11:12:33Z |
| format | Thesis |
| id | mit-1721.1/118084 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T11:12:33Z |
| publishDate | 2018 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/1180842019-04-10T11:54:25Z Co-design of on-chip caches and networks for scalable shared-memory many-core CMPs Kwon, Woo Cheol Li-Shiuan Peh. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018. Cataloged from PDF version of thesis. Includes bibliographical references (pages 169-180). Chip Multi-Processors(CMPs) have become mainstream in recent years, providing increased parallelism as core counts scale. While a tiled CMP is widely accepted to be a scalable architecture for the many-core era, on-chip cache organization and coherence are far from solved problems. As the on-chip interconnect directly influences the latency and bandwidth of on-chip cache, scalable interconnect is an essential part of on-chip cache design. On the other hand, optimal design of interconnect can be determined by the traffic forms that it should handle. Thus, on-chip cache organization is inherently interleaved with on-chip interconnect design and vice versa. This dissertation aims to motivate the need for re-organization of on-chip caches to leverage the advancement of on-chip network technology to harness the full potential of future many-core CMPs. Conversely, we argue that on-chip network should also be designed to support specific functionalities required by the on-chip cache. We propose such co-design techniques to offer significant improvement of on-chip cache performance, and thus to provide scalable CMP cache solutions towards future many-core CMPs. The dissertation starts with the problem of remote on-chip cache access latency. Prior locality-aware approaches fundamentally attempt to keep data as close as possible to the requesting cores. In this dissertation, we challenge this design approach by introducing new cache organization that leverages a co-designed on-chip network that allows multi-hop single-cycle traversals. Next, the dissertation moves to cache coherence request ordering. Without built-in ordering capability within the interconnect, cache coherence protocols have to rely on external ordering points. This dissertation proposes a scalable ordered Network-on-Chip which supports ordering of requests for snoopy cache coherence. Lastly, we describe development of a 36-core research prototype chip to demonstrate that the proposed Network-on-Chip enables shared-memory CMPs to be readily scalable to many-core platforms. by Woo Cheol Kwon. Ph. D. 2018-09-17T15:56:48Z 2018-09-17T15:56:48Z 2018 2018 Thesis http://hdl.handle.net/1721.1/118084 1052123963 eng MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission. http://dspace.mit.edu/handle/1721.1/7582 180 pages application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Kwon, Woo Cheol Co-design of on-chip caches and networks for scalable shared-memory many-core CMPs |
| title | Co-design of on-chip caches and networks for scalable shared-memory many-core CMPs |
| title_full | Co-design of on-chip caches and networks for scalable shared-memory many-core CMPs |
| title_fullStr | Co-design of on-chip caches and networks for scalable shared-memory many-core CMPs |
| title_full_unstemmed | Co-design of on-chip caches and networks for scalable shared-memory many-core CMPs |
| title_short | Co-design of on-chip caches and networks for scalable shared-memory many-core CMPs |
| title_sort | co design of on chip caches and networks for scalable shared memory many core cmps |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/118084 |
| work_keys_str_mv | AT kwonwoocheol codesignofonchipcachesandnetworksforscalablesharedmemorymanycorecmps |