Co-design of on-chip caches and networks for scalable shared-memory many-core CMPs

Co-design of on-chip caches and networks for scalable shared-memory many-core CMPs

Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018.

Bibliographic Details
Main Author: Kwon, Woo Cheol
Other Authors: Li-Shiuan Peh.
Format: Thesis
Language:eng
Published: Massachusetts Institute of Technology 2018
Subjects:
Electrical Engineering and Computer Science.
Online Access:http://hdl.handle.net/1721.1/118084

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