Multitrack power factor correction architecture
Single-phase universal-input ac-dc converters are needed in a wide range of applications. This paper presents a novel power factor correction (PFC) architecture that can achieve high power density and high efficiency as a new development of the Multitrack concept [1]. The proposed Multitrack PFC arc...
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| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
IEEE
2019
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| Online Access: | https://hdl.handle.net/1721.1/121768 |
| _version_ | 1811096176315858944 |
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| author | Chen, Minjie Perreault, David J. |
| author2 | Massachusetts Institute of Technology. Research Laboratory of Electronics |
| author_facet | Massachusetts Institute of Technology. Research Laboratory of Electronics Chen, Minjie Perreault, David J. |
| author_sort | Chen, Minjie |
| collection | MIT |
| description | Single-phase universal-input ac-dc converters are needed in a wide range of applications. This paper presents a novel power factor correction (PFC) architecture that can achieve high power density and high efficiency as a new development of the Multitrack concept [1]. The proposed Multitrack PFC architecture reduces the internal device voltage stress of the power converter subsystems, allowing PFC circuits to maintain zero-voltage-switching (ZVS) at high frequencies (HF, 1-3 MHz) across universal input voltage range (85Vac-265Vac) and wide power range. The high performance of the power converter is enabled by delivering power in multiple stacked voltage domains and reconfiguring the power processing paths depending on the input voltage. This Multitrack concept is compatible with a wide range of existing design techniques for PFC systems. A prototype 150W, universal ac input, 12VDC output, isolated Multitrack PFC system with a power density of 50W/inch3 and a peak end-to-end efficiency of 92% has been built and tested to verify the effectiveness of the Multitrack PFC architecture. |
| first_indexed | 2024-09-23T16:39:25Z |
| format | Article |
| id | mit-1721.1/121768 |
| institution | Massachusetts Institute of Technology |
| language | English |
| last_indexed | 2024-09-23T16:39:25Z |
| publishDate | 2019 |
| publisher | IEEE |
| record_format | dspace |
| spelling | mit-1721.1/1217682022-09-29T20:36:37Z Multitrack power factor correction architecture Chen, Minjie Perreault, David J. Massachusetts Institute of Technology. Research Laboratory of Electronics Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Single-phase universal-input ac-dc converters are needed in a wide range of applications. This paper presents a novel power factor correction (PFC) architecture that can achieve high power density and high efficiency as a new development of the Multitrack concept [1]. The proposed Multitrack PFC architecture reduces the internal device voltage stress of the power converter subsystems, allowing PFC circuits to maintain zero-voltage-switching (ZVS) at high frequencies (HF, 1-3 MHz) across universal input voltage range (85Vac-265Vac) and wide power range. The high performance of the power converter is enabled by delivering power in multiple stacked voltage domains and reconfiguring the power processing paths depending on the input voltage. This Multitrack concept is compatible with a wide range of existing design techniques for PFC systems. A prototype 150W, universal ac input, 12VDC output, isolated Multitrack PFC system with a power density of 50W/inch3 and a peak end-to-end efficiency of 92% has been built and tested to verify the effectiveness of the Multitrack PFC architecture. Texas Instruments Incorporated Center for Intelligent Control Systems (U.S.) Princeton University. Andlinger Center for Energy and the Environment Siebel Energy Institute 2019-07-18T17:46:36Z 2019-07-18T17:46:36Z 2019-03 2019-07-01T15:55:21Z Article http://purl.org/eprint/type/ConferencePaper 0885-8993 https://hdl.handle.net/1721.1/121768 Chen, Minjie, Sombuddha Chakraborty and David J. Perreault. "Multitrack Power Factor Correction Architecture." IEEE Transactions on Power Electronics 34, no.3 (March 2019): pp. 2454-2466 © 2018 The Author(s) en 10.1109/apec.2018.8341094 IEEE Transactions on Power Electronics Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf IEEE other univ website |
| spellingShingle | Chen, Minjie Perreault, David J. Multitrack power factor correction architecture |
| title | Multitrack power factor correction architecture |
| title_full | Multitrack power factor correction architecture |
| title_fullStr | Multitrack power factor correction architecture |
| title_full_unstemmed | Multitrack power factor correction architecture |
| title_short | Multitrack power factor correction architecture |
| title_sort | multitrack power factor correction architecture |
| url | https://hdl.handle.net/1721.1/121768 |
| work_keys_str_mv | AT chenminjie multitrackpowerfactorcorrectionarchitecture AT perreaultdavidj multitrackpowerfactorcorrectionarchitecture |