Virtual wires--overcoming pin limitations in FPGA-based logic emulation
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2005
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| Online Access: | http://hdl.handle.net/1721.1/12274 |
| _version_ | 1826215912132313088 |
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| author | Babb, Jonathan William |
| author2 | Anant Agarwal. |
| author_facet | Anant Agarwal. Babb, Jonathan William |
| author_sort | Babb, Jonathan William |
| collection | MIT |
| description | Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994. |
| first_indexed | 2024-09-23T16:38:59Z |
| format | Thesis |
| id | mit-1721.1/12274 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T16:38:59Z |
| publishDate | 2005 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/122742019-04-12T12:05:27Z Virtual wires--overcoming pin limitations in FPGA-based logic emulation Babb, Jonathan William Anant Agarwal. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science Electrical Engineering and Computer Science Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994. Includes bibliographical references (p. 99-102). by Jonathan William Babb. M.S. 2005-08-16T20:13:22Z 2005-08-16T20:13:22Z 1994 1994 Thesis http://hdl.handle.net/1721.1/12274 30804738 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 102 p. 6213764 bytes 6213523 bytes application/pdf application/pdf application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science Babb, Jonathan William Virtual wires--overcoming pin limitations in FPGA-based logic emulation |
| title | Virtual wires--overcoming pin limitations in FPGA-based logic emulation |
| title_full | Virtual wires--overcoming pin limitations in FPGA-based logic emulation |
| title_fullStr | Virtual wires--overcoming pin limitations in FPGA-based logic emulation |
| title_full_unstemmed | Virtual wires--overcoming pin limitations in FPGA-based logic emulation |
| title_short | Virtual wires--overcoming pin limitations in FPGA-based logic emulation |
| title_sort | virtual wires overcoming pin limitations in fpga based logic emulation |
| topic | Electrical Engineering and Computer Science |
| url | http://hdl.handle.net/1721.1/12274 |
| work_keys_str_mv | AT babbjonathanwilliam virtualwiresovercomingpinlimitationsinfpgabasedlogicemulation |