FAB: Toward Flow-aware Buffer Sharing on Programmable Switches
Conventional buffer sizing techniques consider an output port with multiple queues in isolation and provide guidelines for the size of the queue. In practice, however, switches consist of several ports that share a buffering chip. Hence, chip manufacturers, such as Broadcom, are left to devise a set...
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| Other Authors: | |
| Format: | Article |
| Language: | English |
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ACM
2021
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| Online Access: | https://hdl.handle.net/1721.1/129525 |
| _version_ | 1826206667878957056 |
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| author | Ranjan, Manya |
| author2 | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory |
| author_facet | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory Ranjan, Manya |
| author_sort | Ranjan, Manya |
| collection | MIT |
| description | Conventional buffer sizing techniques consider an output port with multiple queues in isolation and provide guidelines for the size of the queue. In practice, however, switches consist of several ports that share a buffering chip. Hence, chip manufacturers, such as Broadcom, are left to devise a set of proprietary resource sharing algorithms to allocate buffers across ports. This algorithm dynamically adjusts the buffer size for output queues and directly impacts the packet loss and latency of individual queues. We show that the problem of allocating buffers across ports, although less known, is indeed responsible for fundamental inefficiencies in today's devices. In particular, the per-port buffer allocation is an ad-hoc decision that (at best) depends on the remaining buffer cells on the chip instead of the type of traffic. In this work, we advocate for a flow-aware and device-wide buffer sharing scheme (FAB), which is practical today in programmable devices. We tested FAB on two specific workloads and showed that it can improve the tail flow completion time by an order of magnitude compared to conventional buffer management techniques. |
| first_indexed | 2024-09-23T13:36:24Z |
| format | Article |
| id | mit-1721.1/129525 |
| institution | Massachusetts Institute of Technology |
| language | English |
| last_indexed | 2024-09-23T13:36:24Z |
| publishDate | 2021 |
| publisher | ACM |
| record_format | dspace |
| spelling | mit-1721.1/1295252022-10-01T16:00:53Z FAB: Toward Flow-aware Buffer Sharing on Programmable Switches Ranjan, Manya Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory Conventional buffer sizing techniques consider an output port with multiple queues in isolation and provide guidelines for the size of the queue. In practice, however, switches consist of several ports that share a buffering chip. Hence, chip manufacturers, such as Broadcom, are left to devise a set of proprietary resource sharing algorithms to allocate buffers across ports. This algorithm dynamically adjusts the buffer size for output queues and directly impacts the packet loss and latency of individual queues. We show that the problem of allocating buffers across ports, although less known, is indeed responsible for fundamental inefficiencies in today's devices. In particular, the per-port buffer allocation is an ad-hoc decision that (at best) depends on the remaining buffer cells on the chip instead of the type of traffic. In this work, we advocate for a flow-aware and device-wide buffer sharing scheme (FAB), which is practical today in programmable devices. We tested FAB on two specific workloads and showed that it can improve the tail flow completion time by an order of magnitude compared to conventional buffer management techniques. 2021-01-22T14:55:09Z 2021-01-22T14:55:09Z 2019-12 2020-12-15T16:03:36Z Article http://purl.org/eprint/type/ConferencePaper 9781450377454 https://hdl.handle.net/1721.1/129525 Apostolaki, Maria et al. “FAB: Toward Flow-aware Buffer Sharing on Programmable Switches.” Paper in the BS '19, Proceedings of the 2019 Workshop on Buffer Sizing, Palo Alto, Calif., December 2019, ACM: 1-6 © 2019 The Author(s) en 10.1145/3375235.3375237 BS '19 Proceedings of the 2019 Workshop on Buffer Sizing Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf ACM MIT web domain |
| spellingShingle | Ranjan, Manya FAB: Toward Flow-aware Buffer Sharing on Programmable Switches |
| title | FAB: Toward Flow-aware Buffer Sharing on Programmable Switches |
| title_full | FAB: Toward Flow-aware Buffer Sharing on Programmable Switches |
| title_fullStr | FAB: Toward Flow-aware Buffer Sharing on Programmable Switches |
| title_full_unstemmed | FAB: Toward Flow-aware Buffer Sharing on Programmable Switches |
| title_short | FAB: Toward Flow-aware Buffer Sharing on Programmable Switches |
| title_sort | fab toward flow aware buffer sharing on programmable switches |
| url | https://hdl.handle.net/1721.1/129525 |
| work_keys_str_mv | AT ranjanmanya fabtowardflowawarebuffersharingonprogrammableswitches |