Bandwidth steering in HPC using silicon nanophotonics
As bytes-per-FLOP ratios continue to decline, communication is becoming a bottleneck for performance scaling. This paper describes bandwidth steering in HPC using emerging reconfigurable silicon photonic switches. We demonstrate that placing photonics in the lower layers of a hierarchical topology e...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
Association for Computing Machinery (ACM)
2021
|
| Online Access: | https://hdl.handle.net/1721.1/129527 |
| _version_ | 1826197387098456064 |
|---|---|
| author | Ghobadi, Manya |
| author2 | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory |
| author_facet | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory Ghobadi, Manya |
| author_sort | Ghobadi, Manya |
| collection | MIT |
| description | As bytes-per-FLOP ratios continue to decline, communication is becoming a bottleneck for performance scaling. This paper describes bandwidth steering in HPC using emerging reconfigurable silicon photonic switches. We demonstrate that placing photonics in the lower layers of a hierarchical topology efficiently changes the connectivity and consequently allows operators to recover from system fragmentation that is otherwise hard to mitigate using common task placement strategies. Bandwidth steering enables efficient utilization of the higher layers of the topology and reduces cost with no performance penalties. In our simulations with a few thousand network endpoints, bandwidth steering reduces static power consumption per unit throughput by 36% and dynamic power consumption by 14% compared to a reference fat tree topology. Such improvements magnify as we taper the bandwidth of the upper network layer. In our hardware testbed, bandwidth steering improves total application execution time by 69%, unaffected by bandwidth tapering. |
| first_indexed | 2024-09-23T10:47:16Z |
| format | Article |
| id | mit-1721.1/129527 |
| institution | Massachusetts Institute of Technology |
| language | English |
| last_indexed | 2024-09-23T10:47:16Z |
| publishDate | 2021 |
| publisher | Association for Computing Machinery (ACM) |
| record_format | dspace |
| spelling | mit-1721.1/1295272022-09-30T23:01:07Z Bandwidth steering in HPC using silicon nanophotonics Ghobadi, Manya Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory As bytes-per-FLOP ratios continue to decline, communication is becoming a bottleneck for performance scaling. This paper describes bandwidth steering in HPC using emerging reconfigurable silicon photonic switches. We demonstrate that placing photonics in the lower layers of a hierarchical topology efficiently changes the connectivity and consequently allows operators to recover from system fragmentation that is otherwise hard to mitigate using common task placement strategies. Bandwidth steering enables efficient utilization of the higher layers of the topology and reduces cost with no performance penalties. In our simulations with a few thousand network endpoints, bandwidth steering reduces static power consumption per unit throughput by 36% and dynamic power consumption by 14% compared to a reference fat tree topology. Such improvements magnify as we taper the bandwidth of the upper network layer. In our hardware testbed, bandwidth steering improves total application execution time by 69%, unaffected by bandwidth tapering. United States. Advanced Research Projects Agency-Energy. ENLITENED Program (Project award DE-AR00000843) United States. Department of Energy. Office of Science ( Contract DE-AC02-05CH11231) 2021-01-22T16:08:46Z 2021-01-22T16:08:46Z 2019-11 2020-12-15T15:52:27Z Article http://purl.org/eprint/type/ConferencePaper 2167-4329 https://hdl.handle.net/1721.1/129527 Michelogiannakis, George et al. “Bandwidth steering in HPC using silicon nanophotonics.” International Conference for High Performance Computing, Networking, Storage and Analysis, SC, 2019 (November 2019): 17–22 © 2019 The Author(s) en 10.1145/3295500.3356145 International Conference for High Performance Computing, Networking, Storage and Analysis, SC Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf Association for Computing Machinery (ACM) MIT web domain |
| spellingShingle | Ghobadi, Manya Bandwidth steering in HPC using silicon nanophotonics |
| title | Bandwidth steering in HPC using silicon nanophotonics |
| title_full | Bandwidth steering in HPC using silicon nanophotonics |
| title_fullStr | Bandwidth steering in HPC using silicon nanophotonics |
| title_full_unstemmed | Bandwidth steering in HPC using silicon nanophotonics |
| title_short | Bandwidth steering in HPC using silicon nanophotonics |
| title_sort | bandwidth steering in hpc using silicon nanophotonics |
| url | https://hdl.handle.net/1721.1/129527 |
| work_keys_str_mv | AT ghobadimanya bandwidthsteeringinhpcusingsiliconnanophotonics |