Bandwidth steering in HPC using silicon nanophotonics
As bytes-per-FLOP ratios continue to decline, communication is becoming a bottleneck for performance scaling. This paper describes bandwidth steering in HPC using emerging reconfigurable silicon photonic switches. We demonstrate that placing photonics in the lower layers of a hierarchical topology e...
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| Format: | Article |
| Language: | English |
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Association for Computing Machinery (ACM)
2021
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| Online Access: | https://hdl.handle.net/1721.1/129527 |