A 12-Gb/s Stacked Dual-Channel Interface for CMOS Image Sensor Systems
© 2018 by the authors. Licensee MDPI, Basel, Switzerland. We propose a dual-channel interface architecture that allocates high and low transition-density bit streams to two separate channels. The transmitter utilizes the stacked drivers with charge-recycling to reduce the power consumption. The dire...
| Main Authors: | , , , , , |
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| Format: | Article |
| Published: |
2021
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| Online Access: | https://hdl.handle.net/1721.1/132163 |
| _version_ | 1811076404372045824 |
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| author | Kim, Sang-Hoon Shin, Hoon Jeong, Youngkyun Lee, June-Hee Choi, Jaehyuk Chun, Jung-Hoon |
| author_facet | Kim, Sang-Hoon Shin, Hoon Jeong, Youngkyun Lee, June-Hee Choi, Jaehyuk Chun, Jung-Hoon |
| author_sort | Kim, Sang-Hoon |
| collection | MIT |
| description | © 2018 by the authors. Licensee MDPI, Basel, Switzerland. We propose a dual-channel interface architecture that allocates high and low transition-density bit streams to two separate channels. The transmitter utilizes the stacked drivers with charge-recycling to reduce the power consumption. The direct current (DC)-coupled receiver front-end circuits manage the common-mode level variations and compensate for the channel loss. The tracked oversampling clock and data recovery (CDR), which realizes fast lock acquisition below 1 baud period and low logic latency, is shared by the two channels. Fabricated in a 65-nm low-power complementary metal-oxide semiconductor (CMOS) technology, the dual-channel transceiver achieves 12-Gb/s data rate while the transmitter consumes 20.43 mW from a 1.2-V power supply. |
| first_indexed | 2024-09-23T10:21:14Z |
| format | Article |
| id | mit-1721.1/132163 |
| institution | Massachusetts Institute of Technology |
| last_indexed | 2024-09-23T10:21:14Z |
| publishDate | 2021 |
| record_format | dspace |
| spelling | mit-1721.1/1321632022-03-31T14:31:24Z A 12-Gb/s Stacked Dual-Channel Interface for CMOS Image Sensor Systems Kim, Sang-Hoon Shin, Hoon Jeong, Youngkyun Lee, June-Hee Choi, Jaehyuk Chun, Jung-Hoon © 2018 by the authors. Licensee MDPI, Basel, Switzerland. We propose a dual-channel interface architecture that allocates high and low transition-density bit streams to two separate channels. The transmitter utilizes the stacked drivers with charge-recycling to reduce the power consumption. The direct current (DC)-coupled receiver front-end circuits manage the common-mode level variations and compensate for the channel loss. The tracked oversampling clock and data recovery (CDR), which realizes fast lock acquisition below 1 baud period and low logic latency, is shared by the two channels. Fabricated in a 65-nm low-power complementary metal-oxide semiconductor (CMOS) technology, the dual-channel transceiver achieves 12-Gb/s data rate while the transmitter consumes 20.43 mW from a 1.2-V power supply. 2021-09-20T18:21:12Z 2021-09-20T18:21:12Z 2019-02-15T15:19:35Z Article http://purl.org/eprint/type/JournalArticle 1424-8220 https://hdl.handle.net/1721.1/132163 Kim, Sang-Hoon, Hoon Shin, Youngkyun Jeong, June-Hee Lee, Jaehyuk Choi, and Jung-Hoon Chun. “A 12-Gb/s Stacked Dual-Channel Interface for CMOS Image Sensor Systems.” Sensors 18, no. 8 (August 17, 2018): 2709. doi:10.3390/s18082709. http://dx.doi.org/10.3390/s18082709 Sensors Creative Commons Attribution 4.0 International license https://creativecommons.org/licenses/by/4.0/ application/pdf MDPI |
| spellingShingle | Kim, Sang-Hoon Shin, Hoon Jeong, Youngkyun Lee, June-Hee Choi, Jaehyuk Chun, Jung-Hoon A 12-Gb/s Stacked Dual-Channel Interface for CMOS Image Sensor Systems |
| title | A 12-Gb/s Stacked Dual-Channel Interface for CMOS Image Sensor Systems |
| title_full | A 12-Gb/s Stacked Dual-Channel Interface for CMOS Image Sensor Systems |
| title_fullStr | A 12-Gb/s Stacked Dual-Channel Interface for CMOS Image Sensor Systems |
| title_full_unstemmed | A 12-Gb/s Stacked Dual-Channel Interface for CMOS Image Sensor Systems |
| title_short | A 12-Gb/s Stacked Dual-Channel Interface for CMOS Image Sensor Systems |
| title_sort | 12 gb s stacked dual channel interface for cmos image sensor systems |
| url | https://hdl.handle.net/1721.1/132163 |
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