A 32-Unit 240-GHz Heterodyne Receiver Array in 65-nm CMOS With Array-Wide Phase Locking
© 1966-2012 IEEE. This paper reports a 32-unit phase-locked dense heterodyne receiver array at fmathrm RF=240 GHz. To synthesize a large receiving aperture without large sidelobe response, this chip has the following two features. The first feature is the small size of the heterodyne receiver unit,...
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| Format: | Article |
| Language: | English |
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Institute of Electrical and Electronics Engineers (IEEE)
2021
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| Online Access: | https://hdl.handle.net/1721.1/135180 |
| _version_ | 1826199994872365056 |
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| author | Hu, Zhi Wang, Cheng Han, Ruonan |
| author_facet | Hu, Zhi Wang, Cheng Han, Ruonan |
| author_sort | Hu, Zhi |
| collection | MIT |
| description | © 1966-2012 IEEE. This paper reports a 32-unit phase-locked dense heterodyne receiver array at fmathrm RF=240 GHz. To synthesize a large receiving aperture without large sidelobe response, this chip has the following two features. The first feature is the small size of the heterodyne receiver unit, which is only λfRF/4× λfRF/2. It allows for the integration of two interleaved 4× 4 arrays within a 1.2 mm2 die area for concurrent steering of two independent beams. Such unit compactness is enabled by the multi-functionality of the receiver structure, which simultaneously accomplishes local oscillator (LO) generation, inter-unit LO synchronization, input wave coupling, and frequency downconversion. The second feature is the high scalability of the array, which is based on a strongly coupled 2-D LO network. Large array size is realizable simply by tiling more receiver units. With the upscaling of the array, our de-centralized design, contrary to its prior centralized counterparts, offers invariant conversion loss and lower LO phase noise. Meanwhile, the entire LO network is also locked to a 75-MHz reference, facilitating phase-coherent pairing with external sub-terahertz transmitters. A chip prototype using a bulk 65-nm CMOS technology is implemented, with a dc power of 980 mW. Phase locking of the 240-GHz LO is achieved among all 32 units, with a measured phase noise of -84 dBc/Hz (1-MHz offset). The measured sensitivity (BW = 1 kHz) of a single unit is 58 fW. Compared to previous square-law detector arrays of comparable scale and density, this chip provides phase-sensitive detection with 4300× sensitivity improvement. |
| first_indexed | 2024-09-23T11:29:04Z |
| format | Article |
| id | mit-1721.1/135180 |
| institution | Massachusetts Institute of Technology |
| language | English |
| last_indexed | 2024-09-23T11:29:04Z |
| publishDate | 2021 |
| publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| record_format | dspace |
| spelling | mit-1721.1/1351802022-03-31T14:23:06Z A 32-Unit 240-GHz Heterodyne Receiver Array in 65-nm CMOS With Array-Wide Phase Locking Hu, Zhi Wang, Cheng Han, Ruonan © 1966-2012 IEEE. This paper reports a 32-unit phase-locked dense heterodyne receiver array at fmathrm RF=240 GHz. To synthesize a large receiving aperture without large sidelobe response, this chip has the following two features. The first feature is the small size of the heterodyne receiver unit, which is only λfRF/4× λfRF/2. It allows for the integration of two interleaved 4× 4 arrays within a 1.2 mm2 die area for concurrent steering of two independent beams. Such unit compactness is enabled by the multi-functionality of the receiver structure, which simultaneously accomplishes local oscillator (LO) generation, inter-unit LO synchronization, input wave coupling, and frequency downconversion. The second feature is the high scalability of the array, which is based on a strongly coupled 2-D LO network. Large array size is realizable simply by tiling more receiver units. With the upscaling of the array, our de-centralized design, contrary to its prior centralized counterparts, offers invariant conversion loss and lower LO phase noise. Meanwhile, the entire LO network is also locked to a 75-MHz reference, facilitating phase-coherent pairing with external sub-terahertz transmitters. A chip prototype using a bulk 65-nm CMOS technology is implemented, with a dc power of 980 mW. Phase locking of the 240-GHz LO is achieved among all 32 units, with a measured phase noise of -84 dBc/Hz (1-MHz offset). The measured sensitivity (BW = 1 kHz) of a single unit is 58 fW. Compared to previous square-law detector arrays of comparable scale and density, this chip provides phase-sensitive detection with 4300× sensitivity improvement. 2021-10-27T20:11:07Z 2021-10-27T20:11:07Z 2019 2019-05-30T18:15:17Z Article http://purl.org/eprint/type/JournalArticle https://hdl.handle.net/1721.1/135180 en 10.1109/JSSC.2019.2893231 IEEE Journal of Solid-State Circuits Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf Institute of Electrical and Electronics Engineers (IEEE) MIT web domain |
| spellingShingle | Hu, Zhi Wang, Cheng Han, Ruonan A 32-Unit 240-GHz Heterodyne Receiver Array in 65-nm CMOS With Array-Wide Phase Locking |
| title | A 32-Unit 240-GHz Heterodyne Receiver Array in 65-nm CMOS With Array-Wide Phase Locking |
| title_full | A 32-Unit 240-GHz Heterodyne Receiver Array in 65-nm CMOS With Array-Wide Phase Locking |
| title_fullStr | A 32-Unit 240-GHz Heterodyne Receiver Array in 65-nm CMOS With Array-Wide Phase Locking |
| title_full_unstemmed | A 32-Unit 240-GHz Heterodyne Receiver Array in 65-nm CMOS With Array-Wide Phase Locking |
| title_short | A 32-Unit 240-GHz Heterodyne Receiver Array in 65-nm CMOS With Array-Wide Phase Locking |
| title_sort | 32 unit 240 ghz heterodyne receiver array in 65 nm cmos with array wide phase locking |
| url | https://hdl.handle.net/1721.1/135180 |
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