A Common Backend for Hardware Acceleration on FPGA
© 2017 IEEE. Field Programmable Gate Arrays (FPGAs) are configurable integrated circuits able to provide a good trade-off in terms of performance, power consumption, and flexibility with respect to other architectures, like CPUs, GPUs and ASICs. The main drawback in using FPGAs, however, is their st...
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| Format: | Article |
| Language: | English |
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IEEE
2021
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| Online Access: | https://hdl.handle.net/1721.1/137268 |
| _version_ | 1826215915723685888 |
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| author | Del Sozzo, Emanuele Baghdadi, Riyadh Amarasinghe, Saman Santambrogio, Marco D. |
| author_facet | Del Sozzo, Emanuele Baghdadi, Riyadh Amarasinghe, Saman Santambrogio, Marco D. |
| author_sort | Del Sozzo, Emanuele |
| collection | MIT |
| description | © 2017 IEEE. Field Programmable Gate Arrays (FPGAs) are configurable integrated circuits able to provide a good trade-off in terms of performance, power consumption, and flexibility with respect to other architectures, like CPUs, GPUs and ASICs. The main drawback in using FPGAs, however, is their steep learning curve. An emerging solution to this problem is to write algorithms in a Domain Specific Language (DSL) and to let the DSL compiler generate efficient code targeting FPGAs. This work proposes FROST, a unified backend that enables different DSL compilers to target FPGA architectures. Differently from other code generation frameworks targeting FPGA, FROST exploits a scheduling co-language that enables users to have full control over which optimizations to apply in order to generate efficient code (e.g. loop pipelining, array partitioning, vectorization). At first, FROST analyzes and manipulates the input Abstract Syntax Tree (AST) in order to apply FPGA-oriented transformations and optimizations, then generates a C/C++ implementation suitable for High-Level Synthesis (HLS) tools. Finally, the output of HLS phase is synthesized and implemented on the target FPGA using Xilinx SDAccel toolchain. The experimental results show a speedup up of 15 with respect to O3-optimized implementations of the same algorithms on CPU. |
| first_indexed | 2024-09-23T16:39:03Z |
| format | Article |
| id | mit-1721.1/137268 |
| institution | Massachusetts Institute of Technology |
| language | English |
| last_indexed | 2024-09-23T16:39:03Z |
| publishDate | 2021 |
| publisher | IEEE |
| record_format | dspace |
| spelling | mit-1721.1/1372682021-11-04T03:02:01Z A Common Backend for Hardware Acceleration on FPGA Del Sozzo, Emanuele Baghdadi, Riyadh Amarasinghe, Saman Santambrogio, Marco D. © 2017 IEEE. Field Programmable Gate Arrays (FPGAs) are configurable integrated circuits able to provide a good trade-off in terms of performance, power consumption, and flexibility with respect to other architectures, like CPUs, GPUs and ASICs. The main drawback in using FPGAs, however, is their steep learning curve. An emerging solution to this problem is to write algorithms in a Domain Specific Language (DSL) and to let the DSL compiler generate efficient code targeting FPGAs. This work proposes FROST, a unified backend that enables different DSL compilers to target FPGA architectures. Differently from other code generation frameworks targeting FPGA, FROST exploits a scheduling co-language that enables users to have full control over which optimizations to apply in order to generate efficient code (e.g. loop pipelining, array partitioning, vectorization). At first, FROST analyzes and manipulates the input Abstract Syntax Tree (AST) in order to apply FPGA-oriented transformations and optimizations, then generates a C/C++ implementation suitable for High-Level Synthesis (HLS) tools. Finally, the output of HLS phase is synthesized and implemented on the target FPGA using Xilinx SDAccel toolchain. The experimental results show a speedup up of 15 with respect to O3-optimized implementations of the same algorithms on CPU. 2021-11-03T17:52:40Z 2021-11-03T17:52:40Z 2017-11 2019-05-02T17:07:53Z Article http://purl.org/eprint/type/ConferencePaper https://hdl.handle.net/1721.1/137268 Del Sozzo, Emanuele, Baghdadi, Riyadh, Amarasinghe, Saman and Santambrogio, Marco D. 2017. "A Common Backend for Hardware Acceleration on FPGA." en 10.1109/iccd.2017.75 Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf IEEE MIT web domain |
| spellingShingle | Del Sozzo, Emanuele Baghdadi, Riyadh Amarasinghe, Saman Santambrogio, Marco D. A Common Backend for Hardware Acceleration on FPGA |
| title | A Common Backend for Hardware Acceleration on FPGA |
| title_full | A Common Backend for Hardware Acceleration on FPGA |
| title_fullStr | A Common Backend for Hardware Acceleration on FPGA |
| title_full_unstemmed | A Common Backend for Hardware Acceleration on FPGA |
| title_short | A Common Backend for Hardware Acceleration on FPGA |
| title_sort | common backend for hardware acceleration on fpga |
| url | https://hdl.handle.net/1721.1/137268 |
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