dRMT: Disaggregated Programmable Switching
© 2017 ACM. We present dRMT (disaggregated Reconfigurable Match-Action Table), a new architecture for programmable switches. dRMT overcomes two important restrictions of RMT, the predominant pipelinebased architecture for programmable switches: (1) table memory is local to an RMT pipeline stage, imp...
| Main Authors: | , , , , , , , , , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | English |
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Association for Computing Machinery (ACM)
2021
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| Online Access: | https://hdl.handle.net/1721.1/137433 |
| _version_ | 1826212951946690560 |
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| author | Chole, Sharad Fingerhut, Andy Ma, Sha Sivaraman, Anirudh Vargaftik, Shay Berger, Alon Mendelson, Gal Alizadeh, Mohammad Chuang, Shang-Tse Keslassy, Isaac Orda, Ariel Edsall, Tom |
| author2 | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory |
| author_facet | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory Chole, Sharad Fingerhut, Andy Ma, Sha Sivaraman, Anirudh Vargaftik, Shay Berger, Alon Mendelson, Gal Alizadeh, Mohammad Chuang, Shang-Tse Keslassy, Isaac Orda, Ariel Edsall, Tom |
| author_sort | Chole, Sharad |
| collection | MIT |
| description | © 2017 ACM. We present dRMT (disaggregated Reconfigurable Match-Action Table), a new architecture for programmable switches. dRMT overcomes two important restrictions of RMT, the predominant pipelinebased architecture for programmable switches: (1) table memory is local to an RMT pipeline stage, implying that memory not used by one stage cannot be reclaimed by another, and (2) RMT is hardwired to always sequentially execute matches followed by actions as packets traverse pipeline stages. We show that these restrictions make it difficult to execute programs efficiently on RMT. dRMT resolves both issues by disaggregating the memory and compute resources of a programmable switch. Specifically, dRMT moves table memories out of pipeline stages and into a centralized pool that is accessible through a crossbar. In addition, dRMT replaces RMT's pipeline stages with a cluster of processors that can execute match and action operations in any order. We show how to schedule a P4 program on dRMT at compile time to guarantee deterministic throughput and latency. We also present a hardware design for dRMT and analyze its feasibility and chip area. Our results show that dRMT can run programs at line rate with fewer processors compared to RMT, and avoids performance cliffs when there are not enough processors to run a program at line rate. dRMT's hardware design incurs a modest increase in chip area relative to RMT, mainly due to the crossbar. |
| first_indexed | 2024-09-23T15:40:45Z |
| format | Article |
| id | mit-1721.1/137433 |
| institution | Massachusetts Institute of Technology |
| language | English |
| last_indexed | 2024-09-23T15:40:45Z |
| publishDate | 2021 |
| publisher | Association for Computing Machinery (ACM) |
| record_format | dspace |
| spelling | mit-1721.1/1374332023-01-19T16:51:32Z dRMT: Disaggregated Programmable Switching Chole, Sharad Fingerhut, Andy Ma, Sha Sivaraman, Anirudh Vargaftik, Shay Berger, Alon Mendelson, Gal Alizadeh, Mohammad Chuang, Shang-Tse Keslassy, Isaac Orda, Ariel Edsall, Tom Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science © 2017 ACM. We present dRMT (disaggregated Reconfigurable Match-Action Table), a new architecture for programmable switches. dRMT overcomes two important restrictions of RMT, the predominant pipelinebased architecture for programmable switches: (1) table memory is local to an RMT pipeline stage, implying that memory not used by one stage cannot be reclaimed by another, and (2) RMT is hardwired to always sequentially execute matches followed by actions as packets traverse pipeline stages. We show that these restrictions make it difficult to execute programs efficiently on RMT. dRMT resolves both issues by disaggregating the memory and compute resources of a programmable switch. Specifically, dRMT moves table memories out of pipeline stages and into a centralized pool that is accessible through a crossbar. In addition, dRMT replaces RMT's pipeline stages with a cluster of processors that can execute match and action operations in any order. We show how to schedule a P4 program on dRMT at compile time to guarantee deterministic throughput and latency. We also present a hardware design for dRMT and analyze its feasibility and chip area. Our results show that dRMT can run programs at line rate with fewer processors compared to RMT, and avoids performance cliffs when there are not enough processors to run a program at line rate. dRMT's hardware design incurs a modest increase in chip area relative to RMT, mainly due to the crossbar. 2021-11-05T12:15:00Z 2021-11-05T12:15:00Z 2017-08 2020-11-23T18:43:34Z Article http://purl.org/eprint/type/ConferencePaper https://hdl.handle.net/1721.1/137433 Chole, Sharad, Fingerhut, Andy, Ma, Sha, Sivaraman, Anirudh, Vargaftik, Shay et al. 2017. "dRMT: Disaggregated Programmable Switching." SIGCOMM 2017 - Proceedings of the 2017 Conference of the ACM Special Interest Group on Data Communication. en 10.1145/3098822.3098823 SIGCOMM 2017 - Proceedings of the 2017 Conference of the ACM Special Interest Group on Data Communication Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf Association for Computing Machinery (ACM) MIT web domain |
| spellingShingle | Chole, Sharad Fingerhut, Andy Ma, Sha Sivaraman, Anirudh Vargaftik, Shay Berger, Alon Mendelson, Gal Alizadeh, Mohammad Chuang, Shang-Tse Keslassy, Isaac Orda, Ariel Edsall, Tom dRMT: Disaggregated Programmable Switching |
| title | dRMT: Disaggregated Programmable Switching |
| title_full | dRMT: Disaggregated Programmable Switching |
| title_fullStr | dRMT: Disaggregated Programmable Switching |
| title_full_unstemmed | dRMT: Disaggregated Programmable Switching |
| title_short | dRMT: Disaggregated Programmable Switching |
| title_sort | drmt disaggregated programmable switching |
| url | https://hdl.handle.net/1721.1/137433 |
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