Efficient Algorithms, Protocols and Hardware Architectures for Next-Generation Cryptography in Embedded Systems
The Internet of Things (IoT) consists of an ever-growing network of wireless-connected electronic devices which are always collecting, processing and communicating data. While the IoT has inspired many new applications, these embedded devices have unique security challenges, thus making IoT security...
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| Format: | Thesis |
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Massachusetts Institute of Technology
2022
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| Online Access: | https://hdl.handle.net/1721.1/139330 https://orcid.org/0000-0001-7949-4178 |
| _version_ | 1826210576607477760 |
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| author | Banerjee, Utsav |
| author2 | Chandrakasan, Anantha P. |
| author_facet | Chandrakasan, Anantha P. Banerjee, Utsav |
| author_sort | Banerjee, Utsav |
| collection | MIT |
| description | The Internet of Things (IoT) consists of an ever-growing network of wireless-connected electronic devices which are always collecting, processing and communicating data. While the IoT has inspired many new applications, these embedded devices have unique security challenges, thus making IoT security a major concern. Security architectures for IoT devices, both software and hardware, must be low-power and have low energy consumption, while still providing strong cryptographic guarantees and side-channel resilience. Network security protocols use a variety of cryptographic algorithms to achieve these goals. However, the associated computational complexity makes it extremely important to have low-power and energy-efficient embedded implementations of cryptography, especially public key algorithms.
The research presented in this thesis demonstrates the design, implementation and experimental validation of efficient next-generation cryptography for embedded systems using software optimization, hardware acceleration and software-hardware co-design, along with side-channel countermeasures. Using circuit, architecture and algorithm techniques, efficient hardware-accelerated implementations of elliptic curve cryptography, pairing-based cryptography, lattice-based cryptography and other post-quantum cryptography algorithms are demonstrated with up to two orders of magnitude energy savings compared to state-of-the-art software and hardware. These configurable hardware accelerators are further coupled with a low-power micro-processor to provide the flexibility to implement a wide variety of security protocols, thus enabling strong and affordable security for energy-limited IoT nodes. |
| first_indexed | 2024-09-23T14:51:51Z |
| format | Thesis |
| id | mit-1721.1/139330 |
| institution | Massachusetts Institute of Technology |
| last_indexed | 2024-09-23T14:51:51Z |
| publishDate | 2022 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/1393302022-01-15T03:14:48Z Efficient Algorithms, Protocols and Hardware Architectures for Next-Generation Cryptography in Embedded Systems Banerjee, Utsav Chandrakasan, Anantha P. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science The Internet of Things (IoT) consists of an ever-growing network of wireless-connected electronic devices which are always collecting, processing and communicating data. While the IoT has inspired many new applications, these embedded devices have unique security challenges, thus making IoT security a major concern. Security architectures for IoT devices, both software and hardware, must be low-power and have low energy consumption, while still providing strong cryptographic guarantees and side-channel resilience. Network security protocols use a variety of cryptographic algorithms to achieve these goals. However, the associated computational complexity makes it extremely important to have low-power and energy-efficient embedded implementations of cryptography, especially public key algorithms. The research presented in this thesis demonstrates the design, implementation and experimental validation of efficient next-generation cryptography for embedded systems using software optimization, hardware acceleration and software-hardware co-design, along with side-channel countermeasures. Using circuit, architecture and algorithm techniques, efficient hardware-accelerated implementations of elliptic curve cryptography, pairing-based cryptography, lattice-based cryptography and other post-quantum cryptography algorithms are demonstrated with up to two orders of magnitude energy savings compared to state-of-the-art software and hardware. These configurable hardware accelerators are further coupled with a low-power micro-processor to provide the flexibility to implement a wide variety of security protocols, thus enabling strong and affordable security for energy-limited IoT nodes. Ph.D. 2022-01-14T15:04:29Z 2022-01-14T15:04:29Z 2021-06 2021-06-23T19:34:35.016Z Thesis https://hdl.handle.net/1721.1/139330 https://orcid.org/0000-0001-7949-4178 In Copyright - Educational Use Permitted Copyright MIT http://rightsstatements.org/page/InC-EDU/1.0/ application/pdf Massachusetts Institute of Technology |
| spellingShingle | Banerjee, Utsav Efficient Algorithms, Protocols and Hardware Architectures for Next-Generation Cryptography in Embedded Systems |
| title | Efficient Algorithms, Protocols and Hardware Architectures for Next-Generation Cryptography in Embedded Systems |
| title_full | Efficient Algorithms, Protocols and Hardware Architectures for Next-Generation Cryptography in Embedded Systems |
| title_fullStr | Efficient Algorithms, Protocols and Hardware Architectures for Next-Generation Cryptography in Embedded Systems |
| title_full_unstemmed | Efficient Algorithms, Protocols and Hardware Architectures for Next-Generation Cryptography in Embedded Systems |
| title_short | Efficient Algorithms, Protocols and Hardware Architectures for Next-Generation Cryptography in Embedded Systems |
| title_sort | efficient algorithms protocols and hardware architectures for next generation cryptography in embedded systems |
| url | https://hdl.handle.net/1721.1/139330 https://orcid.org/0000-0001-7949-4178 |
| work_keys_str_mv | AT banerjeeutsav efficientalgorithmsprotocolsandhardwarearchitecturesfornextgenerationcryptographyinembeddedsystems |