A high-performance retargetable simulator for parallel architectures
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1991.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2005
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| Online Access: | http://hdl.handle.net/1721.1/13945 |
| _version_ | 1826198172822667264 |
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| author | Dellarocas, Chrysanthos, 1967- |
| author2 | William E. Weihl. |
| author_facet | William E. Weihl. Dellarocas, Chrysanthos, 1967- |
| author_sort | Dellarocas, Chrysanthos, 1967- |
| collection | MIT |
| description | Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1991. |
| first_indexed | 2024-09-23T11:00:20Z |
| format | Thesis |
| id | mit-1721.1/13945 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T11:00:20Z |
| publishDate | 2005 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/139452019-04-12T12:27:56Z A high-performance retargetable simulator for parallel architectures Dellarocas, Chrysanthos, 1967- William E. Weihl. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science Electrical Engineering and Computer Science Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1991. Includes bibliographical references (leaves 94-97). by Chrysanthos Nicholas Dellarocas. M.S. 2005-08-11T12:00:00Z 2005-08-11T12:00:00Z 1991 1991 Thesis http://hdl.handle.net/1721.1/13945 24993035 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 97 leaves 8056821 bytes 8056581 bytes application/pdf application/pdf application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science Dellarocas, Chrysanthos, 1967- A high-performance retargetable simulator for parallel architectures |
| title | A high-performance retargetable simulator for parallel architectures |
| title_full | A high-performance retargetable simulator for parallel architectures |
| title_fullStr | A high-performance retargetable simulator for parallel architectures |
| title_full_unstemmed | A high-performance retargetable simulator for parallel architectures |
| title_short | A high-performance retargetable simulator for parallel architectures |
| title_sort | high performance retargetable simulator for parallel architectures |
| topic | Electrical Engineering and Computer Science |
| url | http://hdl.handle.net/1721.1/13945 |
| work_keys_str_mv | AT dellarocaschrysanthos1967 ahighperformanceretargetablesimulatorforparallelarchitectures AT dellarocaschrysanthos1967 highperformanceretargetablesimulatorforparallelarchitectures |