| Summary: | A Basic, Isolated, Half-Bridge Silicon Carbide Gate Driver was designed and validated using Cadence and SPICE. The architectures of similar gate drivers were studied and simplified to reduce the total area of the gate driver. The fabrication process was also carefully selected to minimize the total area. The gate driver architecture consisted of various analog and mixed signal subcircuits including floating voltage rail generators, inverter chains, and an on-off key receiver among others. Extensive simulations were performed in SPICE and Cadence to analyze the gate driver behavior for various temperature conditions, operating voltages, load conditions, and process corners. The final product was able to drive 6 amps of peak output current, with 10 nanoseconds of propagation delay, and with a 2 milliamp quiescent current.
|
|---|