A Logic Design for the Cell Block of a Data-flow Processor
Recently studies on parallel computation architecture have yielded a new type of computer architecture known as the data-flow processor. As part of the effort in realizing the data-flow processor, a logic design for the Cell Block of the basic data-flow processor is proposed in this thesis. The resu...
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2023
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| Online Access: | https://hdl.handle.net/1721.1/148921 |
| _version_ | 1811082454309535744 |
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| author | Amikura, Katsuhiko |
| author2 | Dennis, Jack B. |
| author_facet | Dennis, Jack B. Amikura, Katsuhiko |
| author_sort | Amikura, Katsuhiko |
| collection | MIT |
| description | Recently studies on parallel computation architecture have yielded a new type of computer architecture known as the data-flow processor. As part of the effort in realizing the data-flow processor, a logic design for the Cell Block of the basic data-flow processor is proposed in this thesis. The resulting design has a modular structure which is derived from a top-down decomposition of the specification given in an Aechitecutere Description Language. The desired speed of operation of the Cell Block is obtained by exploiting the parallellism inherent in its operation. The logic design is carried out using electronic devices available commerically today, but is based on an aynchronous communciation protocol. |
| first_indexed | 2024-09-23T12:03:40Z |
| id | mit-1721.1/148921 |
| institution | Massachusetts Institute of Technology |
| last_indexed | 2024-09-23T12:03:40Z |
| publishDate | 2023 |
| record_format | dspace |
| spelling | mit-1721.1/1489212023-03-30T03:47:09Z A Logic Design for the Cell Block of a Data-flow Processor Amikura, Katsuhiko Dennis, Jack B. Recently studies on parallel computation architecture have yielded a new type of computer architecture known as the data-flow processor. As part of the effort in realizing the data-flow processor, a logic design for the Cell Block of the basic data-flow processor is proposed in this thesis. The resulting design has a modular structure which is derived from a top-down decomposition of the specification given in an Aechitecutere Description Language. The desired speed of operation of the Cell Block is obtained by exploiting the parallellism inherent in its operation. The logic design is carried out using electronic devices available commerically today, but is based on an aynchronous communciation protocol. 2023-03-29T14:09:16Z 2023-03-29T14:09:16Z 1977-12 https://hdl.handle.net/1721.1/148921 3705459 MIT-LCS-TM-093 application/pdf |
| spellingShingle | Amikura, Katsuhiko A Logic Design for the Cell Block of a Data-flow Processor |
| title | A Logic Design for the Cell Block of a Data-flow Processor |
| title_full | A Logic Design for the Cell Block of a Data-flow Processor |
| title_fullStr | A Logic Design for the Cell Block of a Data-flow Processor |
| title_full_unstemmed | A Logic Design for the Cell Block of a Data-flow Processor |
| title_short | A Logic Design for the Cell Block of a Data-flow Processor |
| title_sort | logic design for the cell block of a data flow processor |
| url | https://hdl.handle.net/1721.1/148921 |
| work_keys_str_mv | AT amikurakatsuhiko alogicdesignforthecellblockofadataflowprocessor AT amikurakatsuhiko logicdesignforthecellblockofadataflowprocessor |