Optimizing Synchronous Systems
The complexity of integrated-circuit chips produced today makes it feasible to build inexpensive, special-purpose subsystems that rapidly solve sophisticated problems on behalf of a general-purpose host computer. This paper contributes to the design methodology of efficient VLSI algorithms. We prese...
| Main Authors: | , |
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| Published: |
2023
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| Online Access: | https://hdl.handle.net/1721.1/149025 |
| _version_ | 1826202030877704192 |
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| author | Leiserson, Charles E. Saxe, James B. |
| author_facet | Leiserson, Charles E. Saxe, James B. |
| author_sort | Leiserson, Charles E. |
| collection | MIT |
| description | The complexity of integrated-circuit chips produced today makes it feasible to build inexpensive, special-purpose subsystems that rapidly solve sophisticated problems on behalf of a general-purpose host computer. This paper contributes to the design methodology of efficient VLSI algorithms. We present a transformation that converts synchronous systems into more time-efficient, systolic implementations by removing combinatorial rippling. The problem of determining the optimized system can be reduced to the graph-theoretic single-destination-shortest-paths problem. More importantly from an engineering standpoint, however, the kinds of rippling that can be removed from a circuit at essentially no cost can be easily characterized. For example, if the only global communication in a system is broadcasting from the host computer, the broadcast can always be replaced by local communication. |
| first_indexed | 2024-09-23T12:00:52Z |
| id | mit-1721.1/149025 |
| institution | Massachusetts Institute of Technology |
| last_indexed | 2024-09-23T12:00:52Z |
| publishDate | 2023 |
| record_format | dspace |
| spelling | mit-1721.1/1490252023-03-30T03:47:34Z Optimizing Synchronous Systems Leiserson, Charles E. Saxe, James B. The complexity of integrated-circuit chips produced today makes it feasible to build inexpensive, special-purpose subsystems that rapidly solve sophisticated problems on behalf of a general-purpose host computer. This paper contributes to the design methodology of efficient VLSI algorithms. We present a transformation that converts synchronous systems into more time-efficient, systolic implementations by removing combinatorial rippling. The problem of determining the optimized system can be reduced to the graph-theoretic single-destination-shortest-paths problem. More importantly from an engineering standpoint, however, the kinds of rippling that can be removed from a circuit at essentially no cost can be easily characterized. For example, if the only global communication in a system is broadcasting from the host computer, the broadcast can always be replaced by local communication. 2023-03-29T14:20:37Z 2023-03-29T14:20:37Z 1982-03 https://hdl.handle.net/1721.1/149025 9825255 MIT-LCS-TM-215 application/pdf |
| spellingShingle | Leiserson, Charles E. Saxe, James B. Optimizing Synchronous Systems |
| title | Optimizing Synchronous Systems |
| title_full | Optimizing Synchronous Systems |
| title_fullStr | Optimizing Synchronous Systems |
| title_full_unstemmed | Optimizing Synchronous Systems |
| title_short | Optimizing Synchronous Systems |
| title_sort | optimizing synchronous systems |
| url | https://hdl.handle.net/1721.1/149025 |
| work_keys_str_mv | AT leisersoncharlese optimizingsynchronoussystems AT saxejamesb optimizingsynchronoussystems |