New Lower Bound Techniques For VLSI
In this paper, we use crossing number and wire area arguments to find lower bounds on the layout area and maximum edge length of a variety of new and computationally useful networks. In particular, we describe 1) an N-node planar graph which has layout area ⊖ (NlogN) and maximum edge length ⊖(N^1/2/...
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| Published: |
2023
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| Online Access: | https://hdl.handle.net/1721.1/149037 |