Limitless Directories: A Scalable Cache Coherence Scheme
Caches enhance the performance of multiprocessors by reducing network traffic and average memory access latency. However, cache-based systems must address the problem of cache coherence. We propose the LimitLESS directory protocol to solve this problem. The LimitLESS scheme uses a combination of har...
| Main Authors: | , , |
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| Published: |
2023
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| Online Access: | https://hdl.handle.net/1721.1/149175 |
| _version_ | 1811074865370759168 |
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| author | Chaiken, David Kubiatowicz, John Agarwal, Anant |
| author_facet | Chaiken, David Kubiatowicz, John Agarwal, Anant |
| author_sort | Chaiken, David |
| collection | MIT |
| description | Caches enhance the performance of multiprocessors by reducing network traffic and average memory access latency. However, cache-based systems must address the problem of cache coherence. We propose the LimitLESS directory protocol to solve this problem. The LimitLESS scheme uses a combination of hardware and software techniques to realize the performance of full-map directory with the memory overhead of limited directory. This protocol is supported by Alewife, a large-scale multiprocessor. We describe the architectural interfaces needed to implement the LimitLESS directory, and evaluate its performance though simulations of the Alewife machine. |
| first_indexed | 2024-09-23T09:56:36Z |
| id | mit-1721.1/149175 |
| institution | Massachusetts Institute of Technology |
| last_indexed | 2024-09-23T09:56:36Z |
| publishDate | 2023 |
| record_format | dspace |
| spelling | mit-1721.1/1491752023-03-30T04:06:28Z Limitless Directories: A Scalable Cache Coherence Scheme Chaiken, David Kubiatowicz, John Agarwal, Anant Caches enhance the performance of multiprocessors by reducing network traffic and average memory access latency. However, cache-based systems must address the problem of cache coherence. We propose the LimitLESS directory protocol to solve this problem. The LimitLESS scheme uses a combination of hardware and software techniques to realize the performance of full-map directory with the memory overhead of limited directory. This protocol is supported by Alewife, a large-scale multiprocessor. We describe the architectural interfaces needed to implement the LimitLESS directory, and evaluate its performance though simulations of the Alewife machine. 2023-03-29T14:34:56Z 2023-03-29T14:34:56Z 1991-06 https://hdl.handle.net/1721.1/149175 24101936 MIT-LCS-TM-448 application/pdf |
| spellingShingle | Chaiken, David Kubiatowicz, John Agarwal, Anant Limitless Directories: A Scalable Cache Coherence Scheme |
| title | Limitless Directories: A Scalable Cache Coherence Scheme |
| title_full | Limitless Directories: A Scalable Cache Coherence Scheme |
| title_fullStr | Limitless Directories: A Scalable Cache Coherence Scheme |
| title_full_unstemmed | Limitless Directories: A Scalable Cache Coherence Scheme |
| title_short | Limitless Directories: A Scalable Cache Coherence Scheme |
| title_sort | limitless directories a scalable cache coherence scheme |
| url | https://hdl.handle.net/1721.1/149175 |
| work_keys_str_mv | AT chaikendavid limitlessdirectoriesascalablecachecoherencescheme AT kubiatowiczjohn limitlessdirectoriesascalablecachecoherencescheme AT agarwalanant limitlessdirectoriesascalablecachecoherencescheme |