APRIL: A Processor Architecture for Multiprocessing
Processors in large-scale multiprocessors must be able to tolerate large communication latencies and synchronization delays. This paper describes the architecture of a rapid-context-switching processor called APRIL with support for fine-grain threads and synchronization. APRIL achieves high single-t...
| Main Authors: | , , , |
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| 出版: |
2023
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| 在线阅读: | https://hdl.handle.net/1721.1/149177 |
| _version_ | 1826199857443897344 |
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| author | Agarwal, Anant Lim, Beng-Hong Kranz, David Kubiatowicz, John |
| author_facet | Agarwal, Anant Lim, Beng-Hong Kranz, David Kubiatowicz, John |
| author_sort | Agarwal, Anant |
| collection | MIT |
| description | Processors in large-scale multiprocessors must be able to tolerate large communication latencies and synchronization delays. This paper describes the architecture of a rapid-context-switching processor called APRIL with support for fine-grain threads and synchronization. APRIL achieves high single-thread performance and supports virtual dynamic threads. A commercial RISC-based implementation of APRIL and a run-time software system that can switch contexts in about 10 cycles is described. Measurements taken for several parallel applications on an APRIL simulator show that the overhead for supporting parallel tasks based on futures is reduced by a factor of two over a corresponding implementation on the Encore Multimax. The scalability of a multiprocessor based on APRIL is explored using a performance model. We show that the SPARC-based implementation of APRIL can achieve close to 80% processor utilization with as few as three resident threads per processor in a large-scale cache-based machine with an average base network latency of 55 cycles. |
| first_indexed | 2024-09-23T11:26:55Z |
| id | mit-1721.1/149177 |
| institution | Massachusetts Institute of Technology |
| last_indexed | 2024-09-23T11:26:55Z |
| publishDate | 2023 |
| record_format | dspace |
| spelling | mit-1721.1/1491772023-03-30T03:52:58Z APRIL: A Processor Architecture for Multiprocessing Agarwal, Anant Lim, Beng-Hong Kranz, David Kubiatowicz, John Processors in large-scale multiprocessors must be able to tolerate large communication latencies and synchronization delays. This paper describes the architecture of a rapid-context-switching processor called APRIL with support for fine-grain threads and synchronization. APRIL achieves high single-thread performance and supports virtual dynamic threads. A commercial RISC-based implementation of APRIL and a run-time software system that can switch contexts in about 10 cycles is described. Measurements taken for several parallel applications on an APRIL simulator show that the overhead for supporting parallel tasks based on futures is reduced by a factor of two over a corresponding implementation on the Encore Multimax. The scalability of a multiprocessor based on APRIL is explored using a performance model. We show that the SPARC-based implementation of APRIL can achieve close to 80% processor utilization with as few as three resident threads per processor in a large-scale cache-based machine with an average base network latency of 55 cycles. 2023-03-29T14:35:01Z 2023-03-29T14:35:01Z 1991 https://hdl.handle.net/1721.1/149177 24101716 MIT-LCS-TM-450 application/pdf |
| spellingShingle | Agarwal, Anant Lim, Beng-Hong Kranz, David Kubiatowicz, John APRIL: A Processor Architecture for Multiprocessing |
| title | APRIL: A Processor Architecture for Multiprocessing |
| title_full | APRIL: A Processor Architecture for Multiprocessing |
| title_fullStr | APRIL: A Processor Architecture for Multiprocessing |
| title_full_unstemmed | APRIL: A Processor Architecture for Multiprocessing |
| title_short | APRIL: A Processor Architecture for Multiprocessing |
| title_sort | april a processor architecture for multiprocessing |
| url | https://hdl.handle.net/1721.1/149177 |
| work_keys_str_mv | AT agarwalanant aprilaprocessorarchitectureformultiprocessing AT limbenghong aprilaprocessorarchitectureformultiprocessing AT kranzdavid aprilaprocessorarchitectureformultiprocessing AT kubiatowiczjohn aprilaprocessorarchitectureformultiprocessing |