Dribble-Back Registers: A Technique for Latency Tolerance in Multiprocessors
As parallel machines grow in scale and complexity, latency tolerance of synchronization faults and remote memory accesses becomes increasingly important. One method for tolerating this by multithreading the processor and rapidly context switching between these threads. Fast context switching is most...
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2023
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| Online Access: | https://hdl.handle.net/1721.1/149199 |
| _version_ | 1811090289675206656 |
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| author | Soundararajan, Vijayaraghavan |
| author2 | Agarwal, Anant |
| author_facet | Agarwal, Anant Soundararajan, Vijayaraghavan |
| author_sort | Soundararajan, Vijayaraghavan |
| collection | MIT |
| description | As parallel machines grow in scale and complexity, latency tolerance of synchronization faults and remote memory accesses becomes increasingly important. One method for tolerating this by multithreading the processor and rapidly context switching between these threads. Fast context switching is most effective when the latencies being tolerated are short compared to the total run lengths of all the resident threads. |
| first_indexed | 2024-09-23T14:41:13Z |
| id | mit-1721.1/149199 |
| institution | Massachusetts Institute of Technology |
| last_indexed | 2024-09-23T14:41:13Z |
| publishDate | 2023 |
| record_format | dspace |
| spelling | mit-1721.1/1491992023-03-30T03:23:20Z Dribble-Back Registers: A Technique for Latency Tolerance in Multiprocessors Soundararajan, Vijayaraghavan Agarwal, Anant As parallel machines grow in scale and complexity, latency tolerance of synchronization faults and remote memory accesses becomes increasingly important. One method for tolerating this by multithreading the processor and rapidly context switching between these threads. Fast context switching is most effective when the latencies being tolerated are short compared to the total run lengths of all the resident threads. 2023-03-29T14:36:24Z 2023-03-29T14:36:24Z 1992-06 https://hdl.handle.net/1721.1/149199 27929944 MIT-LCS-TM-474 application/pdf |
| spellingShingle | Soundararajan, Vijayaraghavan Dribble-Back Registers: A Technique for Latency Tolerance in Multiprocessors |
| title | Dribble-Back Registers: A Technique for Latency Tolerance in Multiprocessors |
| title_full | Dribble-Back Registers: A Technique for Latency Tolerance in Multiprocessors |
| title_fullStr | Dribble-Back Registers: A Technique for Latency Tolerance in Multiprocessors |
| title_full_unstemmed | Dribble-Back Registers: A Technique for Latency Tolerance in Multiprocessors |
| title_short | Dribble-Back Registers: A Technique for Latency Tolerance in Multiprocessors |
| title_sort | dribble back registers a technique for latency tolerance in multiprocessors |
| url | https://hdl.handle.net/1721.1/149199 |
| work_keys_str_mv | AT soundararajanvijayaraghavan dribblebackregistersatechniqueforlatencytoleranceinmultiprocessors |