Column-associative Caches: A Technique for Reducing the Miss Rate of Direct-mapped Caches
Direct-mapped caches are a popular design choice for high-performance processors; unfortunately, direct-mapped caches suffer systematic interference misses when more than one address map into the same cache set. This paper describes the design of column-associative caches, which minimize the conflic...
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| Published: |
2023
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| Online Access: | https://hdl.handle.net/1721.1/149210 |