Analyzing Multiprocessor Cache Behavior Through Data Reference Modeling
This paper develops a data reference modeling technique to estimate with high accuracy the cache miss ratio in cache-coherent multiprocessors. The technique involves analyzing the dynamic data referencing behavior of parallel algorithms. Data reference modeling first identifies of different types of...
| Main Authors: | , |
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| Published: |
2023
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| Online Access: | https://hdl.handle.net/1721.1/149216 |
| _version_ | 1826217146199310336 |
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| author | Tsai, Jory Agarwal, Anant |
| author_facet | Tsai, Jory Agarwal, Anant |
| author_sort | Tsai, Jory |
| collection | MIT |
| description | This paper develops a data reference modeling technique to estimate with high accuracy the cache miss ratio in cache-coherent multiprocessors. The technique involves analyzing the dynamic data referencing behavior of parallel algorithms. Data reference modeling first identifies of different types of shared data blocks accessed during the execution of a parallel algorithm, then captures in a few parameters the cache behavior of each shared block as a function of the problem size, number of processors, and cache size, and finally constructs an analytical expression for each algorithm to estimate the cache miss ratio. |
| first_indexed | 2024-09-23T16:58:45Z |
| id | mit-1721.1/149216 |
| institution | Massachusetts Institute of Technology |
| last_indexed | 2024-09-23T16:58:45Z |
| publishDate | 2023 |
| record_format | dspace |
| spelling | mit-1721.1/1492162023-03-30T03:01:59Z Analyzing Multiprocessor Cache Behavior Through Data Reference Modeling Tsai, Jory Agarwal, Anant This paper develops a data reference modeling technique to estimate with high accuracy the cache miss ratio in cache-coherent multiprocessors. The technique involves analyzing the dynamic data referencing behavior of parallel algorithms. Data reference modeling first identifies of different types of shared data blocks accessed during the execution of a parallel algorithm, then captures in a few parameters the cache behavior of each shared block as a function of the problem size, number of processors, and cache size, and finally constructs an analytical expression for each algorithm to estimate the cache miss ratio. 2023-03-29T14:37:23Z 2023-03-29T14:37:23Z 1993-02 https://hdl.handle.net/1721.1/149216 MIT-LCS-TM-497 application/pdf |
| spellingShingle | Tsai, Jory Agarwal, Anant Analyzing Multiprocessor Cache Behavior Through Data Reference Modeling |
| title | Analyzing Multiprocessor Cache Behavior Through Data Reference Modeling |
| title_full | Analyzing Multiprocessor Cache Behavior Through Data Reference Modeling |
| title_fullStr | Analyzing Multiprocessor Cache Behavior Through Data Reference Modeling |
| title_full_unstemmed | Analyzing Multiprocessor Cache Behavior Through Data Reference Modeling |
| title_short | Analyzing Multiprocessor Cache Behavior Through Data Reference Modeling |
| title_sort | analyzing multiprocessor cache behavior through data reference modeling |
| url | https://hdl.handle.net/1721.1/149216 |
| work_keys_str_mv | AT tsaijory analyzingmultiprocessorcachebehaviorthroughdatareferencemodeling AT agarwalanant analyzingmultiprocessorcachebehaviorthroughdatareferencemodeling |