Space - Time Scheduling of Instruction-Level Parallelism on a Raw Machine
Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocessors are ill-suited to exploit such advances. Achieving a high level of parallelism at a reasonable clock speed requires di...
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Bibliographic Details
| Main Authors: |
Lee, Walter,
Barua, R.,
Srikrishna, D.,
Babb, Jonathan,
Sarkar, V.,
Amarasinghe, Saman,
Agarwal, Anant |
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| Published: |
2023
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| Online Access: | https://hdl.handle.net/1721.1/149273
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