Layouts for the Shuffle-exchange Graph and Lower Bound Techniques for VLSI
The thesis is divided into two parts. In the first part, we describe and analyze several new VLSI layouts for the shuffle-exchange graph. These include:1) an asymptotically optimal, (N /log N)-area layout for the N-node shuffle-exchange graph, and 2) several practical layouts for small shuffle...
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2023
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| Online Access: | https://hdl.handle.net/1721.1/149552 |
| _version_ | 1826196873557311488 |
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| author | Leighton, Frank Thomson |
| author2 | Miller, Gary L. |
| author_facet | Miller, Gary L. Leighton, Frank Thomson |
| author_sort | Leighton, Frank Thomson |
| collection | MIT |
| description | The thesis is divided into two parts. In the first part, we describe and analyze several new VLSI layouts for the shuffle-exchange graph. These include:1) an asymptotically optimal, (N /log N)-area layout for the N-node shuffle-exchange graph, and 2) several practical layouts for small shuffle-exchange graphs. |
| first_indexed | 2024-09-23T10:39:19Z |
| id | mit-1721.1/149552 |
| institution | Massachusetts Institute of Technology |
| last_indexed | 2024-09-23T10:39:19Z |
| publishDate | 2023 |
| record_format | dspace |
| spelling | mit-1721.1/1495522023-03-30T04:00:39Z Layouts for the Shuffle-exchange Graph and Lower Bound Techniques for VLSI Leighton, Frank Thomson Miller, Gary L. The thesis is divided into two parts. In the first part, we describe and analyze several new VLSI layouts for the shuffle-exchange graph. These include:1) an asymptotically optimal, (N /log N)-area layout for the N-node shuffle-exchange graph, and 2) several practical layouts for small shuffle-exchange graphs. 2023-03-29T15:06:33Z 2023-03-29T15:06:33Z 1982-08 https://hdl.handle.net/1721.1/149552 19873567 9479447 MIT-LCS-TR-274 application/pdf |
| spellingShingle | Leighton, Frank Thomson Layouts for the Shuffle-exchange Graph and Lower Bound Techniques for VLSI |
| title | Layouts for the Shuffle-exchange Graph and Lower Bound Techniques for VLSI |
| title_full | Layouts for the Shuffle-exchange Graph and Lower Bound Techniques for VLSI |
| title_fullStr | Layouts for the Shuffle-exchange Graph and Lower Bound Techniques for VLSI |
| title_full_unstemmed | Layouts for the Shuffle-exchange Graph and Lower Bound Techniques for VLSI |
| title_short | Layouts for the Shuffle-exchange Graph and Lower Bound Techniques for VLSI |
| title_sort | layouts for the shuffle exchange graph and lower bound techniques for vlsi |
| url | https://hdl.handle.net/1721.1/149552 |
| work_keys_str_mv | AT leightonfrankthomson layoutsfortheshuffleexchangegraphandlowerboundtechniquesforvlsi |