Logic Simulation of a Multiprocessor
The performance of circuit simulators running on SISD computers is fundamentally limited by the Von Neumann bottleneck. Multiprocessors do not share this limitation. The task of solving the equations for the many parallel signal paths found in most circuits lends itself readily to concurrent compu...
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| 出版: |
2023
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| 在线阅读: | https://hdl.handle.net/1721.1/149646 |
| _version_ | 1826202071917920256 |
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| author | Bradley, Elizabeth |
| author_facet | Bradley, Elizabeth |
| author_sort | Bradley, Elizabeth |
| collection | MIT |
| description | The performance of circuit simulators running on SISD computers is fundamentally limited by the Von Neumann bottleneck. Multiprocessors do not share this limitation. The task of solving the equations for the many parallel signal paths found in most circuits lends itself readily to concurrent computation. for both of these reasons, parallel processing is a highly promising approach to circuit simulation. This thesis explores several facets of this problem. |
| first_indexed | 2024-09-23T12:01:45Z |
| id | mit-1721.1/149646 |
| institution | Massachusetts Institute of Technology |
| last_indexed | 2024-09-23T12:01:45Z |
| publishDate | 2023 |
| record_format | dspace |
| spelling | mit-1721.1/1496462023-03-30T03:47:26Z Logic Simulation of a Multiprocessor Bradley, Elizabeth The performance of circuit simulators running on SISD computers is fundamentally limited by the Von Neumann bottleneck. Multiprocessors do not share this limitation. The task of solving the equations for the many parallel signal paths found in most circuits lends itself readily to concurrent computation. for both of these reasons, parallel processing is a highly promising approach to circuit simulation. This thesis explores several facets of this problem. 2023-03-29T15:14:18Z 2023-03-29T15:14:18Z 1986-10 https://hdl.handle.net/1721.1/149646 16953501 MIT-LCS-TR-380 application/pdf |
| spellingShingle | Bradley, Elizabeth Logic Simulation of a Multiprocessor |
| title | Logic Simulation of a Multiprocessor |
| title_full | Logic Simulation of a Multiprocessor |
| title_fullStr | Logic Simulation of a Multiprocessor |
| title_full_unstemmed | Logic Simulation of a Multiprocessor |
| title_short | Logic Simulation of a Multiprocessor |
| title_sort | logic simulation of a multiprocessor |
| url | https://hdl.handle.net/1721.1/149646 |
| work_keys_str_mv | AT bradleyelizabeth logicsimulationofamultiprocessor |