On Retiming Synchronous Circuitry and Mixed-integer Optimization

In this paper we investigate properties of retiming, a circuit transformation which preserves the behavior of the circuit as a whole. We present an algorithm which transforms a given combinational circuit into a functionally equivalent pipelined circuit with minimum latency and clock-period no grea...

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Bibliographic Details
Main Author: Papaefthymiou, Marios Christos
Other Authors: Leiserson, Charles E.
Published: 2023
Online Access:https://hdl.handle.net/1721.1/149695
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author Papaefthymiou, Marios Christos
author2 Leiserson, Charles E.
author_facet Leiserson, Charles E.
Papaefthymiou, Marios Christos
author_sort Papaefthymiou, Marios Christos
collection MIT
description In this paper we investigate properties of retiming, a circuit transformation which preserves the behavior of the circuit as a whole. We present an algorithm which transforms a given combinational circuit into a functionally equivalent pipelined circuit with minimum latency and clock-period no greater than a given upper bound c.
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institution Massachusetts Institute of Technology
last_indexed 2024-09-23T14:12:15Z
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spelling mit-1721.1/1496952023-03-30T03:29:14Z On Retiming Synchronous Circuitry and Mixed-integer Optimization Papaefthymiou, Marios Christos Leiserson, Charles E. In this paper we investigate properties of retiming, a circuit transformation which preserves the behavior of the circuit as a whole. We present an algorithm which transforms a given combinational circuit into a functionally equivalent pipelined circuit with minimum latency and clock-period no greater than a given upper bound c. 2023-03-29T15:17:05Z 2023-03-29T15:17:05Z 1990-09 https://hdl.handle.net/1721.1/149695 22572281 MIT-LCS-TR-486 application/pdf
spellingShingle Papaefthymiou, Marios Christos
On Retiming Synchronous Circuitry and Mixed-integer Optimization
title On Retiming Synchronous Circuitry and Mixed-integer Optimization
title_full On Retiming Synchronous Circuitry and Mixed-integer Optimization
title_fullStr On Retiming Synchronous Circuitry and Mixed-integer Optimization
title_full_unstemmed On Retiming Synchronous Circuitry and Mixed-integer Optimization
title_short On Retiming Synchronous Circuitry and Mixed-integer Optimization
title_sort on retiming synchronous circuitry and mixed integer optimization
url https://hdl.handle.net/1721.1/149695
work_keys_str_mv AT papaefthymioumarioschristos onretimingsynchronouscircuitryandmixedintegeroptimization