Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulation
Existing FPGA-based logic emulators are limited by inter-chip communication bandwidth, resulting in low gate utilization (10 to 20 percent of usable gates). This resource imbalance increases the number of chips needed to emulate a particular logic design and thereby decreases emulation speed, since...
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| Published: |
2023
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| Online Access: | https://hdl.handle.net/1721.1/149751 |
| _version_ | 1826203420659286016 |
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| author | Babb, Jonathan William |
| author2 | Agarwal, Anant |
| author_facet | Agarwal, Anant Babb, Jonathan William |
| author_sort | Babb, Jonathan William |
| collection | MIT |
| description | Existing FPGA-based logic emulators are limited by inter-chip communication bandwidth, resulting in low gate utilization (10 to 20 percent of usable gates). This resource imbalance increases the number of chips needed to emulate a particular logic design and thereby decreases emulation speed, since signals must cross more chip boundaries. |
| first_indexed | 2024-09-23T12:36:42Z |
| id | mit-1721.1/149751 |
| institution | Massachusetts Institute of Technology |
| last_indexed | 2024-09-23T12:36:42Z |
| publishDate | 2023 |
| record_format | dspace |
| spelling | mit-1721.1/1497512023-03-30T03:44:32Z Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulation Babb, Jonathan William Agarwal, Anant Existing FPGA-based logic emulators are limited by inter-chip communication bandwidth, resulting in low gate utilization (10 to 20 percent of usable gates). This resource imbalance increases the number of chips needed to emulate a particular logic design and thereby decreases emulation speed, since signals must cross more chip boundaries. 2023-03-29T15:20:52Z 2023-03-29T15:20:52Z 1993-11 https://hdl.handle.net/1721.1/149751 MIT-LCS-TR-586 application/pdf |
| spellingShingle | Babb, Jonathan William Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulation |
| title | Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulation |
| title_full | Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulation |
| title_fullStr | Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulation |
| title_full_unstemmed | Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulation |
| title_short | Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulation |
| title_sort | virtual wires overcoming pin limitations in fpga based logic emulation |
| url | https://hdl.handle.net/1721.1/149751 |
| work_keys_str_mv | AT babbjonathanwilliam virtualwiresovercomingpinlimitationsinfpgabasedlogicemulation |