Scaling of Nanocryotron Superconducting Logic
This thesis presents the design and characterization of a superconducting shift register based on nanocryotrons. Such a shift register has applications in nanocryotron circuit testing as well as integrated readout and memory for high count rate imagers based on superconducting nanowire single photon...
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| Format: | Thesis |
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Massachusetts Institute of Technology
2023
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| Online Access: | https://hdl.handle.net/1721.1/151424 |
| _version_ | 1826202012699590656 |
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| author | Foster, Reed A. |
| author2 | Berggren, Karl K. |
| author_facet | Berggren, Karl K. Foster, Reed A. |
| author_sort | Foster, Reed A. |
| collection | MIT |
| description | This thesis presents the design and characterization of a superconducting shift register based on nanocryotrons. Such a shift register has applications in nanocryotron circuit testing as well as integrated readout and memory for high count rate imagers based on superconducting nanowire single photon detectors (SNSPDs). Characterization of the shift register shows that it can readily operate in large external magnetic fields that would present a challenge to Josephson-junction-based superconducting technologies. Furthermore, analysis of the input ranges which produce correct operation in a small experimental device suggest that such a circuit may be scalable to millions of nanocryotrons.
A device with a million nanocryotrons would be several orders of magnitude larger than any existing digital circuit based on superconducting nanowires. Development of circuits with more than just a few nanocryotrons has been limited in part due to the difficulty in testing and characterizing these superconducting devices. The absence of standard, well-tested nanocryotron circuits puts the burden of testing on conventional room-temperature electronics such as oscilloscopes and arbitrary waveform generators. However, limited flexibility of on-board computation for preprocessing data handicaps the ability of such systems to characterize larger scale circuits. To address this challenge, this thesis presents a design of an analog frontend for interfacing superconducting circuits with a high speed field-programmable gate array (FPGA) that could automate these tests. |
| first_indexed | 2024-09-23T12:00:28Z |
| format | Thesis |
| id | mit-1721.1/151424 |
| institution | Massachusetts Institute of Technology |
| last_indexed | 2024-09-23T12:00:28Z |
| publishDate | 2023 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/1514242023-08-01T03:49:25Z Scaling of Nanocryotron Superconducting Logic Foster, Reed A. Berggren, Karl K. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science This thesis presents the design and characterization of a superconducting shift register based on nanocryotrons. Such a shift register has applications in nanocryotron circuit testing as well as integrated readout and memory for high count rate imagers based on superconducting nanowire single photon detectors (SNSPDs). Characterization of the shift register shows that it can readily operate in large external magnetic fields that would present a challenge to Josephson-junction-based superconducting technologies. Furthermore, analysis of the input ranges which produce correct operation in a small experimental device suggest that such a circuit may be scalable to millions of nanocryotrons. A device with a million nanocryotrons would be several orders of magnitude larger than any existing digital circuit based on superconducting nanowires. Development of circuits with more than just a few nanocryotrons has been limited in part due to the difficulty in testing and characterizing these superconducting devices. The absence of standard, well-tested nanocryotron circuits puts the burden of testing on conventional room-temperature electronics such as oscilloscopes and arbitrary waveform generators. However, limited flexibility of on-board computation for preprocessing data handicaps the ability of such systems to characterize larger scale circuits. To address this challenge, this thesis presents a design of an analog frontend for interfacing superconducting circuits with a high speed field-programmable gate array (FPGA) that could automate these tests. M.Eng. 2023-07-31T19:38:43Z 2023-07-31T19:38:43Z 2023-06 2023-06-06T16:35:13.408Z Thesis https://hdl.handle.net/1721.1/151424 In Copyright - Educational Use Permitted Copyright retained by author(s) https://rightsstatements.org/page/InC-EDU/1.0/ application/pdf Massachusetts Institute of Technology |
| spellingShingle | Foster, Reed A. Scaling of Nanocryotron Superconducting Logic |
| title | Scaling of Nanocryotron Superconducting Logic |
| title_full | Scaling of Nanocryotron Superconducting Logic |
| title_fullStr | Scaling of Nanocryotron Superconducting Logic |
| title_full_unstemmed | Scaling of Nanocryotron Superconducting Logic |
| title_short | Scaling of Nanocryotron Superconducting Logic |
| title_sort | scaling of nanocryotron superconducting logic |
| url | https://hdl.handle.net/1721.1/151424 |
| work_keys_str_mv | AT fosterreeda scalingofnanocryotronsuperconductinglogic |