Ultra-scaled III-V Vertical Tunneling Transistors
In the quest of reducing the power consumption of transistors, charge carrier transport mechanisms other than thermionic emission over an energy barrier have received considerable attention. Among all possible mechanisms, quantum mechanical tunneling has emerged as one of the most promising, and the...
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| Format: | Thesis |
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Massachusetts Institute of Technology
2023
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| Online Access: | https://hdl.handle.net/1721.1/151619 |
| _version_ | 1826209838200258560 |
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| author | Shao, Yanjie |
| author2 | del Alamo, Jesús A. |
| author_facet | del Alamo, Jesús A. Shao, Yanjie |
| author_sort | Shao, Yanjie |
| collection | MIT |
| description | In the quest of reducing the power consumption of transistors, charge carrier transport mechanisms other than thermionic emission over an energy barrier have received considerable attention. Among all possible mechanisms, quantum mechanical tunneling has emerged as one of the most promising, and the design and demonstration of Tunnel Field-Effect Transistors (TFETs) has been an object of great interest in the past few years. In spite of intense research and promising simulation predictions, the results to date have been disappointing: the combination of high drive current and sub-thermionic switching characteristics has never been achieved. Are we in front of a fundamental barrier?
This thesis is dedicated to exploring the limit of TFETs in terms of device scalability, high-current potential, and sharp switching capability. We focus on the most promising group III-V semiconductor heterojunction structure, the broken-band GaSb/InAsSb system, in a vertical nanowire (VNW) TFET configuration. We first develop a new technology for ultra-scaled GaSb/InAsSb VNW fabrication, reaching a diameter as small as 5 nm. We then build VNW Esaki diodes, demonstrating record-high tunneling current density and ideal scaling behavior. Furthermore, we have fabricated ultra-scaled VNW TFETs which show that a combined high tunneling current and steep subthreshold swing is indeed achievable. Finally, we discuss opportunities and challenges of all-III-V complementary TFET logic. The findings in this thesis demonstrate a potential technology platform for future ultra-low-power digital electronics. |
| first_indexed | 2024-09-23T14:32:12Z |
| format | Thesis |
| id | mit-1721.1/151619 |
| institution | Massachusetts Institute of Technology |
| last_indexed | 2024-09-23T14:32:12Z |
| publishDate | 2023 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/1516192023-08-01T03:21:59Z Ultra-scaled III-V Vertical Tunneling Transistors Shao, Yanjie del Alamo, Jesús A. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science In the quest of reducing the power consumption of transistors, charge carrier transport mechanisms other than thermionic emission over an energy barrier have received considerable attention. Among all possible mechanisms, quantum mechanical tunneling has emerged as one of the most promising, and the design and demonstration of Tunnel Field-Effect Transistors (TFETs) has been an object of great interest in the past few years. In spite of intense research and promising simulation predictions, the results to date have been disappointing: the combination of high drive current and sub-thermionic switching characteristics has never been achieved. Are we in front of a fundamental barrier? This thesis is dedicated to exploring the limit of TFETs in terms of device scalability, high-current potential, and sharp switching capability. We focus on the most promising group III-V semiconductor heterojunction structure, the broken-band GaSb/InAsSb system, in a vertical nanowire (VNW) TFET configuration. We first develop a new technology for ultra-scaled GaSb/InAsSb VNW fabrication, reaching a diameter as small as 5 nm. We then build VNW Esaki diodes, demonstrating record-high tunneling current density and ideal scaling behavior. Furthermore, we have fabricated ultra-scaled VNW TFETs which show that a combined high tunneling current and steep subthreshold swing is indeed achievable. Finally, we discuss opportunities and challenges of all-III-V complementary TFET logic. The findings in this thesis demonstrate a potential technology platform for future ultra-low-power digital electronics. Ph.D. 2023-07-31T19:53:15Z 2023-07-31T19:53:15Z 2023-06 2023-07-13T14:28:16.728Z Thesis https://hdl.handle.net/1721.1/151619 0000-0001-6472-5236 In Copyright - Educational Use Permitted Copyright retained by author(s) https://rightsstatements.org/page/InC-EDU/1.0/ application/pdf Massachusetts Institute of Technology |
| spellingShingle | Shao, Yanjie Ultra-scaled III-V Vertical Tunneling Transistors |
| title | Ultra-scaled III-V Vertical Tunneling Transistors |
| title_full | Ultra-scaled III-V Vertical Tunneling Transistors |
| title_fullStr | Ultra-scaled III-V Vertical Tunneling Transistors |
| title_full_unstemmed | Ultra-scaled III-V Vertical Tunneling Transistors |
| title_short | Ultra-scaled III-V Vertical Tunneling Transistors |
| title_sort | ultra scaled iii v vertical tunneling transistors |
| url | https://hdl.handle.net/1721.1/151619 |
| work_keys_str_mv | AT shaoyanjie ultrascalediiivverticaltunnelingtransistors |