A Continuous-Time Pipeline ADC with Reduced Sensitivity to Clock Jitter
With the advent of the fifth-generation (5G) standard for cellular networks, direct RF receivers are becoming popular in applications such as cellular base stations. Such systems require analog-to-digital converters (ADC) with a high dynamic range over a large digitization bandwidth (> 500 MHz)....
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| Format: | Thesis |
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Massachusetts Institute of Technology
2023
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| Online Access: | https://hdl.handle.net/1721.1/151650 |
| _version_ | 1811088139372986368 |
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| author | Mittal, Rishabh |
| author2 | Lee, Hae-Seung |
| author_facet | Lee, Hae-Seung Mittal, Rishabh |
| author_sort | Mittal, Rishabh |
| collection | MIT |
| description | With the advent of the fifth-generation (5G) standard for cellular networks, direct RF receivers are becoming popular in applications such as cellular base stations. Such systems require analog-to-digital converters (ADC) with a high dynamic range over a large digitization bandwidth (> 500 MHz). For high-speed high-resolution ADCs with an upfront sampler, the clock jitter poses a fundamental bottleneck for the maximum achievable signal-to-noise ratio (SNR). In applications requiring 10-12 bit resolution for 1 GHz digitization bandwidth, the clock jitter values must be no more than a few tens of femtoseconds. This poses significant design challenges for the clock generator.
The continuous-time (CT) pipeline ADC is an emerging architecture that combines the benefits of a discrete-time pipeline ADC and a continuous-time ∆Σ ADC architecture. In this thesis, we explore the clock jitter sensitivity of the CT pipeline ADC. We derive the SNR limitations in a CT pipeline ADC and propose a new CT pipeline ADC design with improved tolerance to clock jitter. We also present a design methodology for the delay line and propose a novel inductor-less delay line that provides a good amplitude and phase matching between the stage 1 signal path and the sub-ADC-DAC path from DC to 1.6 GHz to minimize the signal leakage in the first stage residue.
A prototype ADC was fabricated in a 16-nm FinFET process. The ADC achieves 61.7/60.8dB (low/high frequency) SNR over 1-GHz bandwidth. The active area is 0.77mm² and the ADC consumes 240mW. The Schreier figure-of-merit (FOMS) is 157.9dB which is amongst the best in comparison to other state-of-the-art continuous-time ADCs with digitization bandwidth greater than 500MHz. |
| first_indexed | 2024-09-23T13:56:53Z |
| format | Thesis |
| id | mit-1721.1/151650 |
| institution | Massachusetts Institute of Technology |
| last_indexed | 2024-09-23T13:56:53Z |
| publishDate | 2023 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/1516502023-08-01T03:29:32Z A Continuous-Time Pipeline ADC with Reduced Sensitivity to Clock Jitter Mittal, Rishabh Lee, Hae-Seung Chandrakasan, Anantha P. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science With the advent of the fifth-generation (5G) standard for cellular networks, direct RF receivers are becoming popular in applications such as cellular base stations. Such systems require analog-to-digital converters (ADC) with a high dynamic range over a large digitization bandwidth (> 500 MHz). For high-speed high-resolution ADCs with an upfront sampler, the clock jitter poses a fundamental bottleneck for the maximum achievable signal-to-noise ratio (SNR). In applications requiring 10-12 bit resolution for 1 GHz digitization bandwidth, the clock jitter values must be no more than a few tens of femtoseconds. This poses significant design challenges for the clock generator. The continuous-time (CT) pipeline ADC is an emerging architecture that combines the benefits of a discrete-time pipeline ADC and a continuous-time ∆Σ ADC architecture. In this thesis, we explore the clock jitter sensitivity of the CT pipeline ADC. We derive the SNR limitations in a CT pipeline ADC and propose a new CT pipeline ADC design with improved tolerance to clock jitter. We also present a design methodology for the delay line and propose a novel inductor-less delay line that provides a good amplitude and phase matching between the stage 1 signal path and the sub-ADC-DAC path from DC to 1.6 GHz to minimize the signal leakage in the first stage residue. A prototype ADC was fabricated in a 16-nm FinFET process. The ADC achieves 61.7/60.8dB (low/high frequency) SNR over 1-GHz bandwidth. The active area is 0.77mm² and the ADC consumes 240mW. The Schreier figure-of-merit (FOMS) is 157.9dB which is amongst the best in comparison to other state-of-the-art continuous-time ADCs with digitization bandwidth greater than 500MHz. Ph.D. 2023-07-31T19:56:06Z 2023-07-31T19:56:06Z 2023-06 2023-07-13T14:25:43.879Z Thesis https://hdl.handle.net/1721.1/151650 In Copyright - Educational Use Permitted Copyright retained by author(s) https://rightsstatements.org/page/InC-EDU/1.0/ application/pdf Massachusetts Institute of Technology |
| spellingShingle | Mittal, Rishabh A Continuous-Time Pipeline ADC with Reduced Sensitivity to Clock Jitter |
| title | A Continuous-Time Pipeline ADC with Reduced Sensitivity to Clock Jitter |
| title_full | A Continuous-Time Pipeline ADC with Reduced Sensitivity to Clock Jitter |
| title_fullStr | A Continuous-Time Pipeline ADC with Reduced Sensitivity to Clock Jitter |
| title_full_unstemmed | A Continuous-Time Pipeline ADC with Reduced Sensitivity to Clock Jitter |
| title_short | A Continuous-Time Pipeline ADC with Reduced Sensitivity to Clock Jitter |
| title_sort | continuous time pipeline adc with reduced sensitivity to clock jitter |
| url | https://hdl.handle.net/1721.1/151650 |
| work_keys_str_mv | AT mittalrishabh acontinuoustimepipelineadcwithreducedsensitivitytoclockjitter AT mittalrishabh continuoustimepipelineadcwithreducedsensitivitytoclockjitter |